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Cortex-M0+ CMSIS Definitions
CMSIS Global Defines
Defines and Type Definitions	Type definitions and defines for Cortex-M processor based devices
Status and Control Registers	Core Register type definitions
Nested Vectored Interrupt Controller (NVIC)	Type definitions for the NVIC Registers
System Control Block (SCB)	Type definitions for the System Control Block Registers
System Tick Timer (SysTick)	Type definitions for the System Timer Registers
Core Debug Registers (CoreDebug)	Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file
Core Definitions	Definitions for base addresses, unions, and structures
Functions and Instructions Reference
NVIC Functions	Functions that manage interrupts and exceptions via the NVIC
SysTick Functions	Functions that configure the System
CMSIS Core Register Access Functions
NVIC Functions	Functions that manage interrupts and exceptions via the NVIC
SysTick Functions	Functions that configure the System
CMSIS Core Instruction Interface
FD32M0P Definitions
Device CMSIS Definitions
FD32M0P Peripherals
Analog to Digital Convertor (ADC)
Comparator (COMP)
COMP_REGISTERS
COMP_DESC_REG
COMP_PWR_EN_REG
COMP_RST_CTRL_REG
COMP_RST_STS_REG
COMP_CLK_CTRL_REG
COMP_INTR_STS_REG
COMP_INTR_EVENT_REG
COMP_INTR_EN_REG
COMP_INTR_NMI_EN_REG
COMP_EVENT_EN_REG
COMP_INTR_SW_SET_REG
COMP_STS_REG
COMP_CTRL0_REG
COMP_INPUT_CTRL0_REG
COMP_INPUT_CTRL1_REG
COMP_OUT_CTRL0_REG
COMP_OUT_CTRL1_REG
COMP_REF_CTRL0_REG
COMP_REF_CTRL1_REG
COMP_SPARE_CTRL_REG
COMP_SPARE_STS_REG
COMP_MEMORY_MAP
COMP_KEY
COMP_INTERRUPTS
COMP_REGISTER_FLAGS
Cyclic Redundancy Check (CRC)
CRC_REGISTERS
CRC_PWR_EN_REG
CRC_RST_CTRL_REG
CRC_RST_STS_REG
CRC_CRCCONFIG_REG
CRC_CRCSEED_REG
CRC_CRCINPUT_REG
CRC_CRCRESULT_REG
CRC_MEMORY_MAP
CRC_KEY
CRC_REGISTER_FLAGS
Digital to Analog Convertor (DAC)
DAC_REGISTERS
DAC_DESC_REG
DAC_PWR_EN_REG
DAC_RST_CTRL_REG
DAC_RST_STS_REG
DAC_CLK_CTRL_REG
DAC_INTR_STS_REG
DAC_INTR_EVENT_REG
DAC_INTR_EN_REG
DAC_INTR_NMI_EN_REG
DAC_EVENT_EN_REG
DAC_INTR_SW_SET_REG
DAC_EVENT_CTRL_REG
DAC_CTRL0_REG
DAC_CTRL1_REG
DAC_CTRL2_REG
DAC_CTRL3_REG
DAC_DATA_REG
DAC_CAL_CTRL_REG
DAC_CAL_STS_REG
DAC_SPARE_CTRL_REG
DAC_SPARE_STS_REG
DAC_MEMORY_MAP
DAC_KEY
DAC_INTERRUPTS
DAC_REGISTER_FLAGS
Direct Memory Access (DMA)
DMA_REGISTERS
DMA_DESC_REG
DMA_PWR_EN_REG
DMA_RST_CTRL_REG
DMA_RST_STS_REG
DMA_CLK_CTRL_REG
DMA_DBG_CTRL_REG
DMA_INTR_STS_REG
DMA_INTR_EVENT_REG
DMA_INTR_EN_0_REG
DMA_INTR_EN_1_REG
DMA_INTR_NMI_EN_0_REG
DMA_INTR_NMI_EN_1_REG
DMA_EVENT_EN_0_REG
DMA_EVENT_EN_1_REG
DMA_INTR_SW_SET_REG
DMA_CFG_0_REG
DMA_CFG_1_REG
DMA_CFG_2_REG
DMA_WAITONREQ_REG
DMA_FILL_MODE_REG
DMA_FILL_MODE_CFG_REG
DMA_STRIDE_MODE_REG
DMA_STRIDE_MODE_CFG_0_REG
DMA_STRIDE_MODE_CFG_1_REG
DMA_STRIDE_MODE_CFG_2_REG
DMA_EARLY_IRQ_0_REG
DMA_EARLY_IRQ_1_REG
DMA_EARLY_IRQ_2_REG
DMA_EARLY_IRQ_3_REG
DMA_EARLY_IRQ_4_REG
DMA_EARLY_IRQ_5_REG
DMA_EARLY_IRQ_6_REG
DMA_EARLY_IRQ_7_REG
DMA_EARLY_IRQ_8_REG
DMA_EARLY_IRQ_9_REG
DMA_EARLY_IRQ_10_REG
DMA_EARLY_IRQ_11_REG
DMA_EARLY_IRQ_12_REG
DMA_EARLY_IRQ_13_REG
DMA_EARLY_IRQ_14_REG
DMA_EARLY_IRQ_15_REG
DMA_EARLY_IRQ_CFG_REG
DMA_REPEATED_TRANSFER_EN_REG
DMA_REPEATED_TRANSFER_CHNL_0_REG
DMA_REPEATED_TRANSFER_CHNL_1_REG
DMA_REPEATED_TRANSFER_CHNL_2_REG
DMA_REPEATED_TRANSFER_CHNL_3_REG
DMA_REPEATED_TRANSFER_CHNL_4_REG
DMA_REPEATED_TRANSFER_CHNL_5_REG
DMA_REPEATED_TRANSFER_CHNL_6_REG
DMA_REPEATED_TRANSFER_CHNL_7_REG
DMA_REPEATED_TRANSFER_CHNL_8_REG
DMA_REPEATED_TRANSFER_CHNL_9_REG
DMA_REPEATED_TRANSFER_CHNL_10_REG
DMA_REPEATED_TRANSFER_CHNL_11_REG
DMA_REPEATED_TRANSFER_CHNL_12_REG
DMA_REPEATED_TRANSFER_CHNL_13_REG
DMA_REPEATED_TRANSFER_CHNL_14_REG
DMA_REPEATED_TRANSFER_CHNL_15_REG
DMA_REPEATED_TRANSFER_ALTERNATE_SEL_REG
DMA_ARBITRATION_REG
DMA_ARBITRATION_MASK_REG
DMA_MEMORY_MAP
DMA_KEY
DMA_INTERRUPTS
DMA_REGISTER_FLAGS
Event Fabric
EVENT_FABRIC_REGISTERS
EVENT_FABRIC_DESC_REG
EVENT_FABRIC_PWR_EN_REG
EVENT_FABRIC_RST_CTRL_REG
EVENT_FABRIC_RST_STS_REG
EVENT_FABRIC_CLK_CTRL_REG
EVENT_FABRIC_GEN_PUB_REG
EVENT_FABRIC_GEN_SUB_REG
EVENT_FABRIC_DMA_PUB_REG
EVENT_FABRIC_MEMORY_MAP
EVENT_FABRIC_KEY
EVENT_FABRIC_REGISTER_FLAGS
Flash Memory (FLASH)
FLASH_REGISTERS
FLASH_DESC_REG
FLASH_CLK_CTRL_REG
FLASH_CTRL_REG
FLASH_STATUS_REG
FLASH_TIME_CTRL_REG
FLASH_TIME_CTRL_1_REG
FLASH_TIME_CTRL_2_REG
FLASH_TIME_UPTD_REG
FLASH_HSIZE_CTRL_REG
FLASH_STS_REG
FLASH_ECED_STATUS_REG
FLASH_MEMORY_MAP
FLASH_KEY
FLASH_REGISTER_FLAGS
General Purpose IO (GPIO)
GPIO_REGISTERS
GPIO_DESC_REG
GPIO_PWR_EN_REG
GPIO_RST_CTRL_REG
GPIO_RST_STS_REG
GPIO_CLK_CTRL_REG
GPIO_INTR_STS_REG
GPIO_INTR_EVENT_REG
GPIO_INTR_EN0_REG
GPIO_INTR_EN1_REG
GPIO_INTR_NMI_EN0_REG
GPIO_INTR_NMI_EN1_REG
GPIO_EVENT_EN0_REG
GPIO_EVENT_EN1_REG
GPIO_INTR_SW_SET_REG
GPIO_DOUT_3_0_REG
GPIO_DOUT_7_4_REG
GPIO_DOUT_11_8_REG
GPIO_DOUT_15_12_REG
GPIO_DOUT_19_16_REG
GPIO_DOUT_23_20_REG
GPIO_DOUT_27_24_REG
GPIO_DOUT_31_28_REG
GPIO_DOUT_REG
GPIO_DOUT_SET_REG
GPIO_DOUT_CLR_REG
GPIO_DOUT_TGL_REG
GPIO_DOUT_EN_REG
GPIO_DOUT_EN_SET_REG
GPIO_DOUT_EN_CLR_REG
GPIO_DIN_3_0_REG
GPIO_DIN_7_4_REG
GPIO_DIN_11_8_REG
GPIO_DIN_15_12_REG
GPIO_DIN_19_16_REG
GPIO_DIN_23_20_REG
GPIO_DIN_27_24_REG
GPIO_DIN_31_28_REG
GPIO_DIN_REG
GPIO_FILT_EN_0_REG
GPIO_FILT_EN_1_REG
GPIO_INTR_POL_0_REG
GPIO_INTR_POL_1_REG
GPIO_SUB_CFG_REG
GPIO_DMA_WR_MASK_REG
GPIO_MEMORY_MAP
GPIO_KEY
GPIO_INTERRUPTS
GPIO_REGISTER_FLAGS
GPIO_FILT_EN_REG
GPIO_INTR_POL_REG
I2C
I2C_REGISTERS
I2C_DESC_REG
I2C_PWR_EN_REG
I2C_RST_CTRL_REG
I2C_RST_STS_REG
I2C_CLK_CTRL_REG
I2C_DBG_CTRL_REG
I2C_MASTER_SCL_GEN_REG
I2C_MASTER_TIMING_CONSTRAINT_REG
I2C_MASTER_CLKSTRETCH_CNT_REG
I2C_SLAVE_CLKSTRETCH_CNT_REG
I2C_SMBUS_TIMEOUT_CNT_REG
I2C_INTR_STS_REG
I2C_INTR_EVENT_REG
I2C_INTR_EN_0_REG
I2C_INTR_EN_1_REG
I2C_INTR_NMI_EN_0_REG
I2C_INTR_NMI_EN_1_REG
I2C_RX_DMA_EVENT_EN_0_REG
I2C_RX_DMA_EVENT_EN_1_REG
I2C_TX_DMA_EVENT_EN_0_REG
I2C_TX_DMA_EVENT_EN_1_REG
I2C_INTR_SW_SET_0_REG
I2C_INTR_SW_SET_1_REG
I2C_SPARE_CTRL_REG
I2C_SPARE_STS_REG
I2C_GLITCH_FILTER_CFG_REG
I2C_SLAVE_CTRL_REG
I2C_SLAVE_ADDR_REG
I2C_SLAVE_STS_REG
I2C_SLAVE_ACK_CFG_REG
I2C_SLAVE_BYTE_ACK_REG
I2C_FIFO_CTRL_REG
I2C_RXDATA_REG
I2C_TXDATA_REG
I2C_FIFO_STS_REG
I2C_PEC_CTRL_REG
I2C_PEC_STS_REG
I2C_CRC_OUT_BYTE_REG
I2C_MASTER_CFG_REG
I2C_MASTER_CTRL_REG
I2C_MASTER_ACK_VAL_REG
I2C_MASTER_STS_REG
I2C_MASTER_MON_REG
I2C_FSM_STATUS_REG
I2C_MEMORY_MAP
I2C_KEY
I2C_INTERRUPTS
I2C_REGISTER_FLAGS
IOMUX
MCU_CTRL
Operational Amplifier (OPAMP)
One Time Programmable (OTP)
ARM DMA IP (PL230)
Real Time Clock (RTC)
SPI
SPI_REGISTERS
SPI_DESC_REG
SPI_PWR_EN_REG
SPI_RST_CTRL_REG
SPI_RST_STS_REG
SPI_CLK_CTRL_REG
SPI_CLK_DIV_REG
SPI_CLKSEL_REG
SPI_MOT_MOD_CNTRL_REG
SPI_PARITY_CTRL_REG
SPI_CMD_DATA_CTRL_REG
SPI_LOOPBACK_CTRL_REG
SPI_DATAFRAME_CTRL_REG
SPI_MODE_CTRL_REG
SPI_CS_CTRL_REG
SPI_CS_SETUP_HOLD_CNT_REG
SPI_SCLK_CTRL_REG
SPI_QSPI_CTRL_REG
SPI_DSPI_CTRL_REG
SPI_TX_CTRL_REG
SPI_RX_CTRL_REG
SPI_INT_FIFO_LVL_SEL_REG
SPI_STS_REG
SPI_TX_FIFO_REG
SPI_RX_FIFO_REG
SPI_DBG_CTRL_REG
SPI_INTR_STS_REG
SPI_INTR_EVENT_REG
SPI_INTR_EN_REG
SPI_INTR_TX_DMA_EN_REG
SPI_INTR_RX_DMA_EN_REG
SPI_INTR_NMI_REG
SPI_INTR_SW_SET_REG
SPI_SPARE_CTRL_REG
SPI_SPARE_STS_REG
SPI_MEMORY_MAP
SPI_KEY
SPI_INTERRUPTS
SPI_REGISTER_FLAGS
Timers
TIMER_REGISTERS
TIMER_DESC_REG
TIMER_PWR_EN_REG
TIMER_RST_CTRL_REG
TIMER_RST_STS_REG
TIMER_CLK_CTRL_REG
TIMER_INTR_STS_REG
TIMER_INTR_EVENT_REG
TIMER_INTR_EN_0_REG
TIMER_INTR_EN_1_REG
TIMER_INTR_NMI_EN_0_REG
TIMER_INTR_NMI_EN_1_REG
TIMER_EVENT_EN_0_0_REG
TIMER_EVENT_EN_0_1_REG
TIMER_EVENT_EN_1_0_REG
TIMER_EVENT_EN_1_1_REG
TIMER_INTR_SW_SET_REG
TIMER_EVENT_CTRL_REG
TIMER_CLK_CONFIG_REG
TIMER_TRIG_IN_REG
TIMER_TRIG_OUT_REG
TIMER_INPUT_FILTER_CC_0_REG
TIMER_INPUT_FILTER_CC_1_REG
TIMER_INPUT_FILTER_CC_2_REG
TIMER_INPUT_FILTER_CC_3_REG
TIMER_INPUT_CC_0_REG
TIMER_INPUT_CC_1_REG
TIMER_INPUT_CC_2_REG
TIMER_INPUT_CC_3_REG
TIMER_CC0_CMN_CTRL_REG
TIMER_CC1_CMN_CTRL_REG
TIMER_CC0_CAPTURE_CTRL_REG
TIMER_CC1_CAPTURE_CTRL_REG
TIMER_CC0_COMPARE_CTRL_REG
TIMER_CC1_COMPARE_CTRL_REG
TIMER_CC2_CMN_CTRL_REG
TIMER_CC3_CMN_CTRL_REG
TIMER_CC2_CAPTURE_CTRL_REG
TIMER_CC3_CAPTURE_CTRL_REG
TIMER_CC2_COMPARE_CTRL_REG
TIMER_CC3_COMPARE_CTRL_REG
TIMER_CC4_CMN_CTRL_REG
TIMER_CC5_CMN_CTRL_REG
TIMER_CC4_COMPARE_CTRL_REG
TIMER_CC5_COMPARE_CTRL_REG
TIMER_CC0_CC_PWM_CFG_REG
TIMER_CC1_CC_PWM_CFG_REG
TIMER_CC2_CC_PWM_CFG_REG
TIMER_CC3_CC_PWM_CFG_REG
TIMER_DEADBAND_CFG_REG
TIMER_CC0_OUTPUT_CTL_REG
TIMER_CC1_OUTPUT_CTL_REG
TIMER_CC0_SW_FORCE_REG
TIMER_CC1_SW_FORCE_REG
TIMER_CC2_OUTPUT_CTL_REG
TIMER_CC3_OUTPUT_CTL_REG
TIMER_CC2_SW_FORCE_REG
TIMER_CC3_SW_FORCE_REG
TIMER_FAULT_IN_CTL_REG
TIMER_FAULT_SRC_CTL_REG
TIMER_CTR_CTL_REG
TIMER_CTR_VAL_REG
TIMER_CTR_LOAD_VAL_REG
TIMER_CTR_PL_VAL_REG
TIMER_DEBUG_CTRL_REG
TIMER_RCTR_VAL_REG
TIMER_RCTR_LOAD_VAL_REG
TIMER_QEI_DIR_REG
TIMER_MEMORY_MAP
TIMER_KEY
TIMER_INTERRUPTS
TIMER_REGISTER_FLAGS
UART
UART_REGISTERS
UART_DESC_REG
UART_PWR_EN_REG
UART_RST_CTRL_REG
UART_RST_STS_REG
UART_CLK_CTRL_REG
UART_CLK_SEL_REG
UART_CLK_DIV_REG
UART_DBG_CTRL_REG
UART_INTR_EVENT_REG
UART_INTR_EN0_REG
UART_INTR_EN1_REG
UART_INTR_NMI_EN0_REG
UART_INTR_NMI_EN1_REG
UART_INTR_SW_SET_REG
UART_DMA_RX_EVENT_EN0_REG
UART_DMA_RX_EVENT_EN1_REG
UART_DMA_TX_EVENT_EN0_REG
UART_DMA_TX_EVENT_EN1_REG
UART_INTR_STS_REG
UART_CLKCFG_REG
UART_FIFOLS_REG
UART_FIFOSTS_REG
UART_CFG_REG
UART_GFCTL_REG
UART_TXDATA_REG
UART_RXDATA_REG
UART_BRDNUM_REG
UART_BRDDEN_REG
UART_CTRL_REG
UART_ADDR_REG
UART_ADDRMASK_REG
UART_STS_REG
UART_FSM_STS_REG
UART_MEMORY_MAP
UART_KEY
UART_INTERRUPTS
UART_REGISTER_FLAGS
VREF
VREF_REGISTERS
VREF_DESC_REG
VREF_PWR_EN_REG
VREF_RST_CTRL_REG
VREF_RST_STS_REG
VREF_CLK_CTRL_REG
VREF_STS_REG
VREF_CTRL_REG
VREF_SH_CTRL_REG
VREF_SPARE_CTRL_REG
VREF_SPARE_STS_REG
VREF_MEMORY_MAP
VREF_KEY
VREF_REGISTER_FLAGS
System Control (SYSCTRL)
SYSCTRL_MEMORY_MAP
SYSCTRL_REGISTER_FLAGS
FD32M0P Memory Mapping
FD32M0P Peripheral Declaration
FD32M0P Hardware Abstraction Layer
ADC_HAL
COMP_HAL
CRC_HAL
DAC_HAL
DMA_HAL
EVENT_FABRIC_HAL
FLASH_HAL
GPIO_HAL
SPI_HAL
UART_HAL
VREF_HAL
VULTAN_FLASH_HAL