FD32M0P Microcontroller SDK
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Macros | |
#define | FLASH_BASE (0x00000000UL) |
#define | BOOTROM_BASE (0x01000000UL) |
#define | SRAM_BASE (0x20000000UL) |
#define | PERIPH_BASE (0x3FFC0000UL) |
#define | RAM_BASE (0x20000000UL) |
#define | APB_BASE (0x3FFC0000UL) |
#define | AHB_BASE (0x40000000UL) |
#define | EEPROM_WRITE_BASE (0x00220000UL) |
#define | EEPROM_READ_BASE (0x00009000UL) |
#define | MCU_CTRL_BASE (APB_BASE + 0x00000UL) |
#define | DMA_PL230_BASE (APB_BASE + 0x01000UL) |
#define | DMA_MCU_BASE (APB_BASE + 0x02000UL) |
#define | EVENT_FABRIC_BASE (APB_BASE + 0x03000UL) |
#define | IOMUX_BASE (APB_BASE + 0x04000UL) |
#define | OTP_BASE (APB_BASE + 0x05000UL) |
#define | COMP0_BASE (APB_BASE + 0x06000UL) |
#define | COMP1_BASE (APB_BASE + 0x07000UL) |
#define | COMP2_BASE (APB_BASE + 0x08000UL) |
#define | OPA0_BASE (APB_BASE + 0x09000UL) |
#define | I2C0_BASE (APB_BASE + 0x0A000UL) |
#define | I2C1_BASE (APB_BASE + 0x0B000UL) |
#define | UART0_BASE (APB_BASE + 0x0C000UL) |
#define | RTC_BASE (APB_BASE + 0x0D000UL) |
#define | WDOG0_BASE (APB_BASE + 0x0E000UL) |
#define | WDOG1_BASE (APB_BASE + 0x0F000UL) |
#define | DAC_BASE (APB_BASE + 0x11000UL) |
#define | VREF_BASE (APB_BASE + 0x12000UL) |
#define | UART1_BASE (APB_BASE + 0x13000UL) |
#define | TIMER_A0_BASE (APB_BASE + 0x14000UL) |
#define | TIMER_A1_BASE (APB_BASE + 0x15000UL) |
#define | TIMER_G0_BASE (APB_BASE + 0x16000UL) |
#define | TIMER_G1_BASE (APB_BASE + 0x17000UL) |
#define | VULTAN_APB_BASE (APB_BASE + 0x1B000UL) |
#define | FLASH_APB_BASE (APB_BASE + 0x1C000UL) |
#define | OPA1_BASE (APB_BASE + 0x1D000UL) |
#define | SECURE_IP_BASE (APB_BASE + 0x1E000UL) |
#define | USB2_BASE (APB_BASE + 0x1F000UL) |
#define | GPIO_BASE (AHB_BASE + 0x10000UL) |
#define | SYSCTRL_BASE (AHB_BASE + 0x1F000UL) |
#define | CRC_BASE (AHB_BASE + 0x20000UL) |
#define | SPI_BASE (AHB_BASE + 0x30000UL) |
#define | ADC0_BASE (AHB_BASE + 0x40000UL) |
#define | ADC1_BASE (AHB_BASE + 0x50000UL) |
#define | GPIO_ALIAS_BASE (AHB_BASE + 0x60000UL) |
#define FLASH_BASE (0x00000000UL) |
(FLASH ) Base Address
#define BOOTROM_BASE (0x01000000UL) |
(FLASH ) Base Address
#define SRAM_BASE (0x20000000UL) |
(SRAM ) Base Address
#define PERIPH_BASE (0x3FFC0000UL) |
(Peripheral) Base Address
#define RAM_BASE (0x20000000UL) |
#define APB_BASE (0x3FFC0000UL) |
#define AHB_BASE (0x40000000UL) |
#define EEPROM_WRITE_BASE (0x00220000UL) |
#define EEPROM_READ_BASE (0x00009000UL) |
#define MCU_CTRL_BASE (APB_BASE + 0x00000UL) |
#define DMA_PL230_BASE (APB_BASE + 0x01000UL) |
#define DMA_MCU_BASE (APB_BASE + 0x02000UL) |
#define EVENT_FABRIC_BASE (APB_BASE + 0x03000UL) |
#define IOMUX_BASE (APB_BASE + 0x04000UL) |
#define OTP_BASE (APB_BASE + 0x05000UL) |
#define COMP0_BASE (APB_BASE + 0x06000UL) |
#define COMP1_BASE (APB_BASE + 0x07000UL) |
#define COMP2_BASE (APB_BASE + 0x08000UL) |
#define OPA0_BASE (APB_BASE + 0x09000UL) |
#define I2C0_BASE (APB_BASE + 0x0A000UL) |
#define I2C1_BASE (APB_BASE + 0x0B000UL) |
#define UART0_BASE (APB_BASE + 0x0C000UL) |
#define RTC_BASE (APB_BASE + 0x0D000UL) |
#define WDOG0_BASE (APB_BASE + 0x0E000UL) |
#define WDOG1_BASE (APB_BASE + 0x0F000UL) |
#define DAC_BASE (APB_BASE + 0x11000UL) |
#define VREF_BASE (APB_BASE + 0x12000UL) |
#define UART1_BASE (APB_BASE + 0x13000UL) |
#define TIMER_A0_BASE (APB_BASE + 0x14000UL) |
#define TIMER_A1_BASE (APB_BASE + 0x15000UL) |
#define TIMER_G0_BASE (APB_BASE + 0x16000UL) |
#define TIMER_G1_BASE (APB_BASE + 0x17000UL) |
#define VULTAN_APB_BASE (APB_BASE + 0x1B000UL) |
#define FLASH_APB_BASE (APB_BASE + 0x1C000UL) |
#define OPA1_BASE (APB_BASE + 0x1D000UL) |
#define SECURE_IP_BASE (APB_BASE + 0x1E000UL) |
#define USB2_BASE (APB_BASE + 0x1F000UL) |
#define GPIO_BASE (AHB_BASE + 0x10000UL) |
#define SYSCTRL_BASE (AHB_BASE + 0x1F000UL) |
#define CRC_BASE (AHB_BASE + 0x20000UL) |
#define SPI_BASE (AHB_BASE + 0x30000UL) |
#define ADC0_BASE (AHB_BASE + 0x40000UL) |
#define ADC1_BASE (AHB_BASE + 0x50000UL) |
#define GPIO_ALIAS_BASE (AHB_BASE + 0x60000UL) |