FD32M0P Microcontroller SDK
|
Macros | |
#define | __CM0_REV 0x0000 |
#define | __NVIC_PRIO_BITS 2 |
#define | __Vendor_SysTickConfig 0 |
#define | __MPU_PRESENT 1 |
#define | __VTOR_PRESENT 1 |
Enumerations | |
enum | IRQn_Type { NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , SVCall_IRQn = -5 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WDG0_IRQn = 0 , WDG1_IRQn = 1 , DEBUG_SS_IRQn = 2 , MCU_CTRL_IRQn = 3 , FLASH_IRQn = 4 , GPIO_IRQn = 5 , UNUSED6_IRQn = 6 , COMP0_IRQn = 7 , COMP1_IRQn = 8 , COMP2_IRQn = 9 , ADC0_IRQn = 10 , ADC1_IRQn = 11 , DAC_IRQn = 12 , SPI_IRQn = 13 , UART0_IRQn = 14 , UART1_IRQn = 15 , TIMER_G0_IRQn = 16 , TIMER_A0_IRQn = 17 , TIMER_G1_IRQn = 18 , TIMER_G2_IRQn = 19 , TIMER_G3_IRQn = 20 , TIMER_G4_IRQn = 21 , TIMER_A1_IRQn = 22 , I2C0_IRQn = 23 , I2C1_IRQn = 24 , RTC_IRQn = 25 , DMA_IRQn = 26 , USB2_IRQn = 27 , UNUSED28_IRQn = 28 , UNUSED29_IRQn = 29 , UNUSED30_IRQn = 30 , UNUSED31_IRQn = 31 } |
Configuration of the Cortex-M0+ Processor and Core Peripherals
#define __CM0_REV 0x0000 |
Core Revision r2p1
#define __NVIC_PRIO_BITS 2 |
Number of Bits used for Priority Levels
Referenced by NVIC_GetPriority(), NVIC_SetPriority(), and SysTick_Config().
#define __Vendor_SysTickConfig 0 |
Set to 1 if different SysTick Config is used
#define __MPU_PRESENT 1 |
MPU present or not
#define __VTOR_PRESENT 1 |
Cortex-M0+ can support the VTOR
enum IRQn_Type |