FD32M0P Microcontroller SDK
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
- v -
VREF_BASE :
FD32M0P.h
vref_cfg() :
vref.c
,
vref.h
VREF_CLK_CTRL_CLK_DIV_BY_1 :
VREF_REGS.h
VREF_CLK_CTRL_CLK_DIV_BY_2 :
VREF_REGS.h
VREF_CLK_CTRL_CLK_DIV_BY_3 :
VREF_REGS.h
VREF_CLK_CTRL_CLK_DIV_BY_4 :
VREF_REGS.h
VREF_CLK_CTRL_CLK_DIV_BY_5 :
VREF_REGS.h
VREF_CLK_CTRL_CLK_DIV_BY_6 :
VREF_REGS.h
VREF_CLK_CTRL_CLK_DIV_BY_7 :
VREF_REGS.h
VREF_CLK_CTRL_CLK_DIV_BY_8 :
VREF_REGS.h
VREF_CLK_CTRL_CLK_DIV_E :
VREF_REGS.h
VREF_CLK_CTRL_CLK_DIV_MASK :
VREF_REGS.h
VREF_CLK_CTRL_CLK_DIV_OFS :
VREF_REGS.h
VREF_CLK_CTRL_CLK_SEL_4MHZ :
VREF_REGS.h
VREF_CLK_CTRL_CLK_SEL_APB :
VREF_REGS.h
VREF_CLK_CTRL_CLK_SEL_E :
VREF_REGS.h
VREF_CLK_CTRL_CLK_SEL_LF :
VREF_REGS.h
VREF_CLK_CTRL_CLK_SEL_MASK :
VREF_REGS.h
VREF_CLK_CTRL_CLK_SEL_OFS :
VREF_REGS.h
VREF_CLK_CTRL_WRITE() :
VREF_RW_API.h
VREF_CTRL_ENABLE_MASK :
VREF_REGS.h
VREF_CTRL_ENABLE_OFS :
VREF_REGS.h
VREF_CTRL_SH_EN_MASK :
VREF_REGS.h
VREF_CTRL_SH_EN_OFS :
VREF_REGS.h
VREF_CTRL_VREF_MODE_1P4V :
VREF_REGS.h
VREF_CTRL_VREF_MODE_2P5V :
VREF_REGS.h
VREF_CTRL_VREF_MODE_E :
VREF_REGS.h
VREF_CTRL_VREF_MODE_MASK :
VREF_REGS.h
VREF_CTRL_VREF_MODE_OFS :
VREF_REGS.h
VREF_CTRL_WRITE() :
VREF_RW_API.h
VREF_DESC_MAJOR_REV_MASK :
VREF_REGS.h
VREF_DESC_MAJOR_REV_OFS :
VREF_REGS.h
VREF_DESC_MINOR_REV_MASK :
VREF_REGS.h
VREF_DESC_MINOR_REV_OFS :
VREF_REGS.h
VREF_DESC_MODUE_SUBTYPE_MASK :
VREF_REGS.h
VREF_DESC_MODUE_SUBTYPE_OFS :
VREF_REGS.h
VREF_DESC_MODULE_TYPE_MASK :
VREF_REGS.h
VREF_DESC_MODULE_TYPE_OFS :
VREF_REGS.h
VREF_PWR_EN_PWR_EN_KEY :
VREF_REGS.h
VREF_PWR_EN_PWR_EN_KEY_MASK :
VREF_REGS.h
VREF_PWR_EN_PWR_EN_KEY_OFS :
VREF_REGS.h
VREF_PWR_EN_PWR_EN_MASK :
VREF_REGS.h
VREF_PWR_EN_PWR_EN_OFS :
VREF_REGS.h
VREF_PWR_EN_WRITE() :
VREF_RW_API.h
VREF_REGS :
FD32M0P.h
VREF_RST_CTRL_RST_KEY :
VREF_REGS.h
VREF_RST_CTRL_RST_KEY_MASK :
VREF_REGS.h
VREF_RST_CTRL_RST_KEY_OFS :
VREF_REGS.h
VREF_RST_CTRL_RST_MASK :
VREF_REGS.h
VREF_RST_CTRL_RST_OFS :
VREF_REGS.h
VREF_RST_CTRL_RST_STS_CLR_KEY :
VREF_REGS.h
VREF_RST_CTRL_RST_STS_CLR_MASK :
VREF_REGS.h
VREF_RST_CTRL_RST_STS_CLR_OFS :
VREF_REGS.h
VREF_RST_CTRL_WRITE() :
VREF_RW_API.h
VREF_RST_STS_RST_STS_MASK :
VREF_REGS.h
VREF_RST_STS_RST_STS_OFS :
VREF_REGS.h
VREF_SH_CTRL_HOLD_CNT_MASK :
VREF_REGS.h
VREF_SH_CTRL_HOLD_CNT_OFS :
VREF_REGS.h
VREF_SH_CTRL_PERIOD_CNT_MASK :
VREF_REGS.h
VREF_SH_CTRL_PERIOD_CNT_OFS :
VREF_REGS.h
VREF_SH_CTRL_WRITE() :
VREF_RW_API.h
VREF_SPARE_CTRL_VREF_CFG0_MASK :
VREF_REGS.h
VREF_SPARE_CTRL_VREF_CFG0_OFS :
VREF_REGS.h
VREF_SPARE_CTRL_VREF_CFG1_MASK :
VREF_REGS.h
VREF_SPARE_CTRL_VREF_CFG1_OFS :
VREF_REGS.h
VREF_SPARE_CTRL_WRITE() :
VREF_RW_API.h
VREF_SPARE_STS_VREF_STS0_MASK :
VREF_REGS.h
VREF_SPARE_STS_VREF_STS0_OFS :
VREF_REGS.h
VREF_SPARE_STS_VREF_STS1_MASK :
VREF_REGS.h
VREF_SPARE_STS_VREF_STS1_OFS :
VREF_REGS.h
VREF_STS_VREF_RDY_MASK :
VREF_REGS.h
VREF_STS_VREF_RDY_OFS :
VREF_REGS.h
VULTAN_APB_BASE :
FD32M0P.h
VULTAN_APB_REGS :
FD32M0P.h
VULTAN_FLASH_ADDR_ADDR_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_ADDR_ADDR_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_ADDR_WRITE() :
VULTAN_FLASH_RW_API.h
VULTAN_FLASH_CTRL_ABORT_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_CTRL_ABORT_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_CTRL_CMD_E :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_CTRL_CMD_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_CTRL_CMD_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_CTRL_CMD_READ :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_CTRL_CMD_ROW_WRITE :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_CTRL_CMD_WRITE :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_CTRL_WRITE() :
VULTAN_FLASH_RW_API.h
VULTAN_FLASH_DATA0_DATA0_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_DATA0_DATA0_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_DATA0_WRITE() :
VULTAN_FLASH_RW_API.h
VULTAN_FLASH_DATA1_DATA1_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_DATA1_DATA1_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_DATA2_DATA2_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_DATA2_DATA2_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_DATA3_DATA3_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_DATA3_DATA3_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_CLR_CMD_ACCEPT_IRQ_EN_CLR_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_CLR_CMD_ACCEPT_IRQ_EN_CLR_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_CLR_CMD_FAIL_IRQ_EN_CLR_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_CLR_CMD_FAIL_IRQ_EN_CLR_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_CLR_CMD_REJECT_IRQ_EN_CLR_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_CLR_CMD_REJECT_IRQ_EN_CLR_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_CLR_CMD_SUCCESS_IRQ_EN_CLR_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_CLR_CMD_SUCCESS_IRQ_EN_CLR_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_CLR_READ_OVERFLOW_IRQ_EN_CLR_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_CLR_READ_OVERFLOW_IRQ_EN_CLR_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_CLR_WRITE() :
VULTAN_FLASH_RW_API.h
VULTAN_FLASH_IRQ_ENABLE_SET_CMD_ACCEPT_IRQ_EN_SET_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_SET_CMD_ACCEPT_IRQ_EN_SET_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_SET_CMD_FAIL_IRQ_EN_SET_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_SET_CMD_FAIL_IRQ_EN_SET_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_SET_CMD_REJECT_IRQ_EN_SET_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_SET_CMD_REJECT_IRQ_EN_SET_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_SET_CMD_SUCCESS_IRQ_EN_SET_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_SET_CMD_SUCCESS_IRQ_EN_SET_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_SET_READ_OVERFLOW_IRQ_EN_SET_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_SET_READ_OVERFLOW_IRQ_EN_SET_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_ENABLE_SET_WRITE() :
VULTAN_FLASH_RW_API.h
VULTAN_FLASH_IRQ_MASKED_STATUS_CMD_ACCEPT_IRQ_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_MASKED_STATUS_CMD_ACCEPT_IRQ_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_MASKED_STATUS_CMD_FAIL_IRQ_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_MASKED_STATUS_CMD_FAIL_IRQ_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_MASKED_STATUS_CMD_REJECT_IRQ_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_MASKED_STATUS_CMD_REJECT_IRQ_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_MASKED_STATUS_CMD_SUCCESS_IRQ_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_MASKED_STATUS_CMD_SUCCESS_IRQ_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_MASKED_STATUS_READ_OVERFLOW_IRQ_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_MASKED_STATUS_READ_OVERFLOW_IRQ_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_CLR_CMD_ACCEPT_IRQ_STS_CLR_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_CLR_CMD_ACCEPT_IRQ_STS_CLR_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_CLR_CMD_FAIL_IRQ_STS_CLR_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_CLR_CMD_FAIL_IRQ_STS_CLR_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_CLR_CMD_REJECT_IRQ_STS_CLR_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_CLR_CMD_REJECT_IRQ_STS_CLR_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_CLR_CMD_SUCCESS_IRQ_STS_CLR_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_CLR_CMD_SUCCESS_IRQ_STS_CLR_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_CLR_READ_OVERFLOW_IRQ_STS_CLR_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_CLR_READ_OVERFLOW_IRQ_STS_CLR_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_CLR_WRITE() :
VULTAN_FLASH_RW_API.h
VULTAN_FLASH_IRQ_STATUS_SET_CMD_ACCEPT_IRQ_STS_SET_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_SET_CMD_ACCEPT_IRQ_STS_SET_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_SET_CMD_FAIL_IRQ_STS_SET_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_SET_CMD_FAIL_IRQ_STS_SET_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_SET_CMD_REJECT_IRQ_STS_SET_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_SET_CMD_REJECT_IRQ_STS_SET_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_SET_CMD_SUCCESS_IRQ_STS_SET_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_SET_CMD_SUCCESS_IRQ_STS_SET_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_SET_READ_OVERFLOW_IRQ_STS_SET_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_SET_READ_OVERFLOW_IRQ_STS_SET_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_IRQ_STATUS_SET_WRITE() :
VULTAN_FLASH_RW_API.h
VULTAN_FLASH_REGS_PTR :
vultan_flash.h
VULTAN_FLASH_STATUS_ARBITRATION_LOCKED_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_STATUS_ARBITRATION_LOCKED_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_STATUS_CMD_ACCEPT_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_STATUS_CMD_ACCEPT_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_STATUS_CMD_FAIL_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_STATUS_CMD_FAIL_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_STATUS_CMD_FINISH_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_STATUS_CMD_FINISH_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_STATUS_CMD_PENDING_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_STATUS_CMD_PENDING_OFS :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_STATUS_CMD_SUCCESS_MASK :
VULTAN_FLASH_REGS.h
VULTAN_FLASH_STATUS_CMD_SUCCESS_OFS :
VULTAN_FLASH_REGS.h
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