FD32M0P Microcontroller SDK: Data Fields

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- p -

PA : IOMUX_REGS_s
packed_byte : ADC_BLOCK_ASYNC_REQ_u, ADC_CALIBRATION_REQ_u, ADC_CHNL_CFG_u, ADC_CLK_CTRL_u, ADC_CLK_SEL_u, ADC_CONV_CFG_u, ADC_DBG_CTRL_u, ADC_DESC_u, ADC_DMA_EVENT_EN_0_u, ADC_DMA_EVENT_EN_1_u, ADC_DMA_REG_u, ADC_DMA_TRANSFER_CNT_u, ADC_EOC_ANA_u, ADC_EVENT_EN_0_u, ADC_EVENT_EN_1_u, ADC_HW_AVG_CFG_u, ADC_INTR_EN_0_u, ADC_INTR_EN_1_u, ADC_INTR_EVENT_u, ADC_INTR_NMI_EN_0_u, ADC_INTR_NMI_EN_1_u, ADC_INTR_STS_u, ADC_INTR_SW_u, ADC_POWER_DN_u, ADC_PUBS_PORT_u, ADC_PWR_EN_u, ADC_RESULT_CFG_u, ADC_RESULT_u, ADC_RST_CTRL_u, ADC_RST_STS_u, ADC_SM_STATE_u, ADC_SPARE_CTRL_u, ADC_SPARE_STS_u, ADC_STATUS_u, ADC_SUBS_PORT_u, ADC_SW_TRIGGER_u, ADC_TEMP_SENSOR_EN_u, ADC_TIMER_CONVERSION_u, ADC_TIMER_SAMPLE_u, ADC_TIMER_START_u, ADC_WINDOW_COMP_u, BOOTLOADER_BCR_CFG0_u, BOOTLOADER_BCR_CFG1_u, BOOTLOADER_BCR_CFG2_u, BOOTLOADER_BCR_CONFIG_ID_u, BOOTLOADER_BCR_CRCCFG0_u, BOOTLOADER_BCR_CRCCFG1_u, BOOTLOADER_BCR_CRCCFG2_u, BOOTLOADER_BCR_CRCCFG3_u, BOOTLOADER_BCR_FLASH_WP_u, BOOTLOADER_BSL_CONFIG_ID_u, BOOTLOADER_BSL_I2C_CFG_u, BOOTLOADER_BSL_PWD_u, BOOTLOADER_BSL_UART_CFG0_u, BOOTLOADER_BSL_UART_CFG1_u, COMP_CLK_CTRL_u, COMP_CTRL0_u, COMP_DESC_u, COMP_EVENT_EN_u, COMP_INPUT_CTRL0_u, COMP_INPUT_CTRL1_u, COMP_INTR_EN_u, COMP_INTR_EVENT_u, COMP_INTR_NMI_EN_u, COMP_INTR_STS_u, COMP_INTR_SW_SET_u, COMP_OUT_CTRL0_u, COMP_OUT_CTRL1_u, COMP_PWR_EN_u, COMP_REF_CTRL0_u, COMP_REF_CTRL1_u, COMP_RST_CTRL_u, COMP_RST_STS_u, COMP_SPARE_CTRL_u, COMP_SPARE_STS_u, COMP_STS_u, CRC_CRCCONFIG_u, CRC_CRCINPUT_u, CRC_CRCRESULT_u, CRC_CRCSEED_u, CRC_PWR_EN_u, CRC_RST_CTRL_u, CRC_RST_STS_u, DAC_CAL_CTRL_u, DAC_CAL_STS_u, DAC_CLK_CTRL_u, DAC_CTRL0_u, DAC_CTRL1_u, DAC_CTRL2_u, DAC_CTRL3_u, DAC_DATA_u, DAC_DESC_u, DAC_EVENT_CTRL_u, DAC_EVENT_EN_u, DAC_INTR_EN_u, DAC_INTR_EVENT_u, DAC_INTR_NMI_EN_u, DAC_INTR_STS_u, DAC_INTR_SW_SET_u, DAC_PWR_EN_u, DAC_RST_CTRL_u, DAC_RST_STS_u, DAC_SPARE_CTRL_u, DAC_SPARE_STS_u, DMA_ARBITRATION_MASK_u, DMA_ARBITRATION_u, DMA_CFG_0_u, DMA_CFG_1_u, DMA_CFG_2_u, DMA_CLK_CTRL_u, DMA_DBG_CTRL_u, DMA_DESC_u, DMA_EARLY_IRQ_0_u, DMA_EARLY_IRQ_10_u, DMA_EARLY_IRQ_11_u, DMA_EARLY_IRQ_12_u, DMA_EARLY_IRQ_13_u, DMA_EARLY_IRQ_14_u, DMA_EARLY_IRQ_15_u, DMA_EARLY_IRQ_1_u, DMA_EARLY_IRQ_2_u, DMA_EARLY_IRQ_3_u, DMA_EARLY_IRQ_4_u, DMA_EARLY_IRQ_5_u, DMA_EARLY_IRQ_6_u, DMA_EARLY_IRQ_7_u, DMA_EARLY_IRQ_8_u, DMA_EARLY_IRQ_9_u, DMA_EARLY_IRQ_CFG_u, DMA_EVENT_EN_0_u, DMA_EVENT_EN_1_u, DMA_FILL_MODE_CFG_u, DMA_FILL_MODE_u, DMA_INTR_EN_0_u, DMA_INTR_EN_1_u, DMA_INTR_EVENT_u, DMA_INTR_NMI_EN_0_u, DMA_INTR_NMI_EN_1_u, DMA_INTR_STS_u, DMA_INTR_SW_SET_u, DMA_PWR_EN_u, DMA_REPEATED_TRANSFER_ALTERNATE_SEL_u, DMA_REPEATED_TRANSFER_CHNL_0_u, DMA_REPEATED_TRANSFER_CHNL_10_u, DMA_REPEATED_TRANSFER_CHNL_11_u, DMA_REPEATED_TRANSFER_CHNL_12_u, DMA_REPEATED_TRANSFER_CHNL_13_u, DMA_REPEATED_TRANSFER_CHNL_14_u, DMA_REPEATED_TRANSFER_CHNL_15_u, DMA_REPEATED_TRANSFER_CHNL_1_u, DMA_REPEATED_TRANSFER_CHNL_2_u, DMA_REPEATED_TRANSFER_CHNL_3_u, DMA_REPEATED_TRANSFER_CHNL_4_u, DMA_REPEATED_TRANSFER_CHNL_5_u, DMA_REPEATED_TRANSFER_CHNL_6_u, DMA_REPEATED_TRANSFER_CHNL_7_u, DMA_REPEATED_TRANSFER_CHNL_8_u, DMA_REPEATED_TRANSFER_CHNL_9_u, DMA_REPEATED_TRANSFER_EN_u, DMA_RST_CTRL_u, DMA_RST_STS_u, DMA_STRIDE_MODE_CFG_0_u, DMA_STRIDE_MODE_CFG_1_u, DMA_STRIDE_MODE_CFG_2_u, DMA_STRIDE_MODE_u, DMA_WAITONREQ_u, EVENT_FABRIC_CLK_CTRL_u, EVENT_FABRIC_DESC_u, EVENT_FABRIC_DMA_PUB_u, EVENT_FABRIC_GEN_PUB_u, EVENT_FABRIC_GEN_SUB_u, EVENT_FABRIC_PWR_EN_u, EVENT_FABRIC_RST_CTRL_u, EVENT_FABRIC_RST_STS_u, FLASH_CLK_CTRL_u, FLASH_CTRL_u, FLASH_DESC_u, FLASH_ECED_STATUS_u, FLASH_HSIZE_CTRL_u, FLASH_STATUS_u, FLASH_STS_u, FLASH_TIME_CTRL_1_u, FLASH_TIME_CTRL_2_u, FLASH_TIME_CTRL_u, FLASH_TIME_UPTD_u, GPIO_CLK_CTRL_u, GPIO_DESC_u, GPIO_DIN_11_8_u, GPIO_DIN_15_12_u, GPIO_DIN_19_16_u, GPIO_DIN_23_20_u, GPIO_DIN_27_24_u, GPIO_DIN_31_28_u, GPIO_DIN_3_0_u, GPIO_DIN_7_4_u, GPIO_DIN_u, GPIO_DMA_WR_MASK_u, GPIO_DOUT_11_8_u, GPIO_DOUT_15_12_u, GPIO_DOUT_19_16_u, GPIO_DOUT_23_20_u, GPIO_DOUT_27_24_u, GPIO_DOUT_31_28_u, GPIO_DOUT_3_0_u, GPIO_DOUT_7_4_u, GPIO_DOUT_CLR_u, GPIO_DOUT_EN_CLR_u, GPIO_DOUT_EN_SET_u, GPIO_DOUT_EN_u, GPIO_DOUT_SET_u, GPIO_DOUT_TGL_u, GPIO_DOUT_u, GPIO_EVENT_EN0_u, GPIO_EVENT_EN1_u, GPIO_FILT_EN_0_u, GPIO_FILT_EN_1_u, GPIO_INTR_EN0_u, GPIO_INTR_EN1_u, GPIO_INTR_EVENT_u, GPIO_INTR_NMI_EN0_u, GPIO_INTR_NMI_EN1_u, GPIO_INTR_POL_0_u, GPIO_INTR_POL_1_u, GPIO_INTR_STS_u, GPIO_INTR_SW_SET_u, GPIO_PWR_EN_u, GPIO_RST_CTRL_u, GPIO_RST_STS_u, GPIO_SUB_CFG_u, I2C_CLK_CTRL_u, I2C_CRC_OUT_BYTE_u, I2C_DBG_CTRL_u, I2C_DESC_u, I2C_FIFO_CTRL_u, I2C_FIFO_STS_u, I2C_FSM_STATUS_u, I2C_GLITCH_FILTER_CFG_u, I2C_INTR_EN_0_u, I2C_INTR_EN_1_u, I2C_INTR_EVENT_u, I2C_INTR_NMI_EN_0_u, I2C_INTR_NMI_EN_1_u, I2C_INTR_STS_u, I2C_INTR_SW_SET_0_u, I2C_INTR_SW_SET_1_u, I2C_MASTER_ACK_VAL_u, I2C_MASTER_CFG_u, I2C_MASTER_CLKSTRETCH_CNT_u, I2C_MASTER_CTRL_u, I2C_MASTER_MON_u, I2C_MASTER_SCL_GEN_u, I2C_MASTER_STS_u, I2C_MASTER_TIMING_CONSTRAINT_u, I2C_PEC_CTRL_u, I2C_PEC_STS_u, I2C_PWR_EN_u, I2C_RST_CTRL_u, I2C_RST_STS_u, I2C_RX_DMA_EVENT_EN_0_u, I2C_RX_DMA_EVENT_EN_1_u, I2C_RXDATA_u, I2C_SLAVE_ACK_CFG_u, I2C_SLAVE_ADDR_u, I2C_SLAVE_BYTE_ACK_u, I2C_SLAVE_CLKSTRETCH_CNT_u, I2C_SLAVE_CTRL_u, I2C_SLAVE_STS_u, I2C_SMBUS_TIMEOUT_CNT_u, I2C_SPARE_CTRL_u, I2C_SPARE_STS_u, I2C_TX_DMA_EVENT_EN_0_u, I2C_TX_DMA_EVENT_EN_1_u, I2C_TXDATA_u, IOMUX_DUMMY_u, IOMUX_PA_u, MCU_CTRL_AHB_HCLK_CTRL_u, MCU_CTRL_ANA_CLK_EN_u, MCU_CTRL_ANA_SPARE_OUT0_u, MCU_CTRL_ANA_SPARE_OUT1_u, MCU_CTRL_ANA_SPARE_STS_u, MCU_CTRL_AON_CTRL_u, MCU_CTRL_APB_PCLK_CTRL_u, MCU_CTRL_BLOCK_CLK_REQ_u, MCU_CTRL_BOOT_CFG_u, MCU_CTRL_BOR_MODE_SEL_u, MCU_CTRL_CLK_4MHZ_CTRL_u, MCU_CTRL_CLK_CTRL_u, MCU_CTRL_CLK_PWR_EN_u, MCU_CTRL_DESC_u, MCU_CTRL_GPAMPCTL_u, MCU_CTRL_GPAMPSTS_u, MCU_CTRL_HF_CLK_CTRL_u, MCU_CTRL_HF_OSC_CLK_CTRL_u, MCU_CTRL_INTR_EN_u, MCU_CTRL_INTR_EVENT_u, MCU_CTRL_LF_CLK_CTRL_u, MCU_CTRL_MCU_SW_RST_u, MCU_CTRL_PLL_CTRL1_u, MCU_CTRL_PLL_CTRL2_u, MCU_CTRL_PLL_EN_u, MCU_CTRL_PMODE_CFG_u, MCU_CTRL_PROCMONCTL_u, MCU_CTRL_PWR_SM_OVRD_CTL_u, MCU_CTRL_RST_CTRL_u, MCU_CTRL_RST_STS_u, MCU_CTRL_SPARE_CTRL_u, MCU_CTRL_SPARE_STS_u, MCU_CTRL_XO_CFG_STS_u, OPAMP_CTRL0_u, OPAMP_DESC_u, OPAMP_GAIN_CTRL0_u, OPAMP_INPUT_CTRL0_u, OPAMP_PWR_EN_u, OPAMP_RST_CTRL_u, OPAMP_RST_STS_u, OPAMP_SPARE_CTRL_u, OPAMP_SPARE_STS_u, OTP_OTP_CTRL_u, OTP_OTP_EN_u, OTP_OTP_RD_EN_u, OTP_OTP_RD_STATUS_u, OTP_OTP_STATUS_u, OTP_OTP_u, OTP_STS_u, OTP_TIMER_CTRL_u, PL230_ALT_CTRL_BASE_PTR_u, PL230_CHNL_ENABLE_CLR_u, PL230_CHNL_ENABLE_SET_u, PL230_CHNL_PRI_ALT_CLR_u, PL230_CHNL_PRI_ALT_SET_u, PL230_CHNL_PRIORITY_CLR_u, PL230_CHNL_PRIORITY_SET_u, PL230_CHNL_REQ_MASK_CLR_u, PL230_CHNL_REQ_MASK_SET_u, PL230_CHNL_SW_REQUEST_u, PL230_CHNL_USEBURST_CLR_u, PL230_CHNL_USEBURST_SET_u, PL230_CTRL_BASE_PTR_u, PL230_DMA_CFG_u, PL230_DMA_STATUS_u, PL230_DMA_WAITONREQ_STATUS_u, PL230_ERR_CLR_u, RTC_A0_DAY_u, RTC_A0_HOUR_u, RTC_A0_MIN_u, RTC_A1_DAY_u, RTC_A1_HOUR_u, RTC_A1_MIN_u, RTC_BUS_CLK_FORCE_u, RTC_CLK_CTRL_u, RTC_DEBUG_CTL_u, RTC_DESC_u, RTC_DOM_CTL_u, RTC_DOW_CTL_u, RTC_EVENT_EN_u, RTC_HR_CTL_u, RTC_INTERVAL_INTR_SEL_u, RTC_INTR_EN_u, RTC_INTR_EVENT_u, RTC_INTR_NMI_EN_u, RTC_INTR_STS_u, RTC_INTR_SW_SET_u, RTC_MIN_CTL_u, RTC_MON_CTL_u, RTC_PRD_INTR_SEL0_u, RTC_PRD_INTR_SEL1_u, RTC_PWR_EN_u, RTC_RST_CTRL_u, RTC_RST_STS_u, RTC_RTC_CAL_u, RTC_RTC_CTL_u, RTC_RTC_TEMP_CMP_u, RTC_SEC_CTL_u, RTC_YEAR_CTL_u, SPI_CLK_CTRL_u, SPI_CLK_DIV_u, SPI_CLKSEL_u, SPI_CMD_DATA_CTRL_u, SPI_CS_CTRL_u, SPI_CS_SETUP_HOLD_CNT_u, SPI_DATAFRAME_CTRL_u, SPI_DBG_CTRL_u, SPI_DESC_u, SPI_DSPI_CTRL_u, SPI_INT_FIFO_LVL_SEL_u, SPI_INTR_EN_u, SPI_INTR_EVENT_u, SPI_INTR_NMI_u, SPI_INTR_RX_DMA_EN_u, SPI_INTR_STS_u, SPI_INTR_SW_SET_u, SPI_INTR_TX_DMA_EN_u, SPI_LOOPBACK_CTRL_u, SPI_MODE_CTRL_u, SPI_MOT_MOD_CNTRL_u, SPI_PARITY_CTRL_u, SPI_PWR_EN_u, SPI_QSPI_CTRL_u, SPI_RST_CTRL_u, SPI_RST_STS_u, SPI_RX_CTRL_u, SPI_RX_FIFO_u, SPI_SCLK_CTRL_u, SPI_SPARE_CTRL_u, SPI_SPARE_STS_u, SPI_STS_u, SPI_TX_CTRL_u, SPI_TX_FIFO_u, TIMER_CC0_CAPTURE_CTRL_u, TIMER_CC0_CC_PWM_CFG_u, TIMER_CC0_CMN_CTRL_u, TIMER_CC0_COMPARE_CTRL_u, TIMER_CC0_OUTPUT_CTL_u, TIMER_CC0_SW_FORCE_u, TIMER_CC1_CAPTURE_CTRL_u, TIMER_CC1_CC_PWM_CFG_u, TIMER_CC1_CMN_CTRL_u, TIMER_CC1_COMPARE_CTRL_u, TIMER_CC1_OUTPUT_CTL_u, TIMER_CC1_SW_FORCE_u, TIMER_CC2_CAPTURE_CTRL_u, TIMER_CC2_CC_PWM_CFG_u, TIMER_CC2_CMN_CTRL_u, TIMER_CC2_COMPARE_CTRL_u, TIMER_CC2_OUTPUT_CTL_u, TIMER_CC2_SW_FORCE_u, TIMER_CC3_CAPTURE_CTRL_u, TIMER_CC3_CC_PWM_CFG_u, TIMER_CC3_CMN_CTRL_u, TIMER_CC3_COMPARE_CTRL_u, TIMER_CC3_OUTPUT_CTL_u, TIMER_CC3_SW_FORCE_u, TIMER_CC4_CMN_CTRL_u, TIMER_CC4_COMPARE_CTRL_u, TIMER_CC5_CMN_CTRL_u, TIMER_CC5_COMPARE_CTRL_u, TIMER_CLK_CONFIG_u, TIMER_CLK_CTRL_u, TIMER_CTR_CTL_u, TIMER_CTR_LOAD_VAL_u, TIMER_CTR_PL_VAL_u, TIMER_CTR_VAL_u, TIMER_DEADBAND_CFG_u, TIMER_DEBUG_CTRL_u, TIMER_DESC_u, TIMER_EVENT_CTRL_u, TIMER_EVENT_EN_0_0_u, TIMER_EVENT_EN_0_1_u, TIMER_EVENT_EN_1_0_u, TIMER_EVENT_EN_1_1_u, TIMER_FAULT_IN_CTL_u, TIMER_FAULT_SRC_CTL_u, TIMER_INPUT_CC_0_u, TIMER_INPUT_CC_1_u, TIMER_INPUT_CC_2_u, TIMER_INPUT_CC_3_u, TIMER_INPUT_FILTER_CC_0_u, TIMER_INPUT_FILTER_CC_1_u, TIMER_INPUT_FILTER_CC_2_u, TIMER_INPUT_FILTER_CC_3_u, TIMER_INTR_EN_0_u, TIMER_INTR_EN_1_u, TIMER_INTR_EVENT_u, TIMER_INTR_NMI_EN_0_u, TIMER_INTR_NMI_EN_1_u, TIMER_INTR_STS_u, TIMER_INTR_SW_SET_u, TIMER_PWR_EN_u, TIMER_QEI_DIR_u, TIMER_RCTR_LOAD_VAL_u, TIMER_RCTR_VAL_u, TIMER_RST_CTRL_u, TIMER_RST_STS_u, TIMER_TIMG_NUM_INPUT2_CC0_CAPTURE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_u, TIMER_TIMG_NUM_INPUT2_CC0_CMN_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC0_COMPARE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC0_OUTPUT_CTL_u, TIMER_TIMG_NUM_INPUT2_CC0_SW_FORCE_u, TIMER_TIMG_NUM_INPUT2_CC1_CAPTURE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_u, TIMER_TIMG_NUM_INPUT2_CC1_CMN_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC1_COMPARE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC1_OUTPUT_CTL_u, TIMER_TIMG_NUM_INPUT2_CC1_SW_FORCE_u, TIMER_TIMG_NUM_INPUT2_CLK_CONFIG_u, TIMER_TIMG_NUM_INPUT2_CLK_CTRL_u, TIMER_TIMG_NUM_INPUT2_CTR_CTL_u, TIMER_TIMG_NUM_INPUT2_CTR_LOAD_VAL_u, TIMER_TIMG_NUM_INPUT2_CTR_VAL_u, TIMER_TIMG_NUM_INPUT2_DEBUG_CTRL_u, TIMER_TIMG_NUM_INPUT2_DESC_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_1_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_1_u, TIMER_TIMG_NUM_INPUT2_INPUT_CC_0_u, TIMER_TIMG_NUM_INPUT2_INPUT_CC_1_u, TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_0_u, TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_1_u, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_u, TIMER_TIMG_NUM_INPUT2_INTR_EN_1_u, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_u, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_u, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_1_u, TIMER_TIMG_NUM_INPUT2_INTR_STS_u, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_u, TIMER_TIMG_NUM_INPUT2_PWR_EN_u, TIMER_TIMG_NUM_INPUT2_RST_CTRL_u, TIMER_TIMG_NUM_INPUT2_RST_STS_u, TIMER_TIMG_NUM_INPUT2_TRIG_IN_u, TIMER_TIMG_NUM_INPUT2_TRIG_OUT_u, TIMER_TRIG_IN_u, TIMER_TRIG_OUT_u, UART_ADDR_u, UART_ADDRMASK_u, UART_BRDDEN_u, UART_BRDNUM_u, UART_CFG_u, UART_CLK_CTRL_u, UART_CLK_DIV_u, UART_CLK_SEL_u, UART_CLKCFG_u, UART_CTRL_u, UART_DBG_CTRL_u, UART_DESC_u, UART_DMA_RX_EVENT_EN0_u, UART_DMA_RX_EVENT_EN1_u, UART_DMA_TX_EVENT_EN0_u, UART_DMA_TX_EVENT_EN1_u, UART_FIFOLS_u, UART_FIFOSTS_u, UART_FSM_STS_u, UART_GFCTL_u, UART_INTR_EN0_u, UART_INTR_EN1_u, UART_INTR_EVENT_u, UART_INTR_NMI_EN0_u, UART_INTR_NMI_EN1_u, UART_INTR_STS_u, UART_INTR_SW_SET_u, UART_PWR_EN_u, UART_RST_CTRL_u, UART_RST_STS_u, UART_RXDATA_u, UART_STS_u, UART_TXDATA_u, VREF_CLK_CTRL_u, VREF_CTRL_u, VREF_DESC_u, VREF_PWR_EN_u, VREF_RST_CTRL_u, VREF_RST_STS_u, VREF_SH_CTRL_u, VREF_SPARE_CTRL_u, VREF_SPARE_STS_u, VREF_STS_u, VULTAN_FLASH_ADDR_u, VULTAN_FLASH_CTRL_u, VULTAN_FLASH_DATA0_u, VULTAN_FLASH_DATA1_u, VULTAN_FLASH_DATA2_u, VULTAN_FLASH_DATA3_u, VULTAN_FLASH_IRQ_ENABLE_CLR_u, VULTAN_FLASH_IRQ_ENABLE_SET_u, VULTAN_FLASH_IRQ_MASKED_STATUS_u, VULTAN_FLASH_IRQ_STATUS_CLR_u, VULTAN_FLASH_IRQ_STATUS_SET_u, VULTAN_FLASH_STATUS_u, WATCHDOG_DESC_u, WATCHDOG_EVENT_EN_u, WATCHDOG_HALT_MODE_u, WATCHDOG_INTR_EN_u, WATCHDOG_INTR_EVENT_u, WATCHDOG_INTR_NMI_EN_u, WATCHDOG_INTR_STS_u, WATCHDOG_INTR_SW_SET_u, WATCHDOG_PWR_EN_u, WATCHDOG_RST_CTRL_u, WATCHDOG_RST_STS_u, WATCHDOG_WWDT_CTL0_u, WATCHDOG_WWDT_CTL1_u, WATCHDOG_WWDT_EN_u, WATCHDOG_WWDT_RESTART_u, WATCHDOG_WWDT_STS_u
packed_hw : ADC_BLOCK_ASYNC_REQ_u, ADC_CALIBRATION_REQ_u, ADC_CHNL_CFG_u, ADC_CLK_CTRL_u, ADC_CLK_SEL_u, ADC_CONV_CFG_u, ADC_DBG_CTRL_u, ADC_DESC_u, ADC_DMA_EVENT_EN_0_u, ADC_DMA_EVENT_EN_1_u, ADC_DMA_REG_u, ADC_DMA_TRANSFER_CNT_u, ADC_EOC_ANA_u, ADC_EVENT_EN_0_u, ADC_EVENT_EN_1_u, ADC_HW_AVG_CFG_u, ADC_INTR_EN_0_u, ADC_INTR_EN_1_u, ADC_INTR_EVENT_u, ADC_INTR_NMI_EN_0_u, ADC_INTR_NMI_EN_1_u, ADC_INTR_STS_u, ADC_INTR_SW_u, ADC_POWER_DN_u, ADC_PUBS_PORT_u, ADC_PWR_EN_u, ADC_RESULT_CFG_u, ADC_RESULT_u, ADC_RST_CTRL_u, ADC_RST_STS_u, ADC_SM_STATE_u, ADC_SPARE_CTRL_u, ADC_SPARE_STS_u, ADC_STATUS_u, ADC_SUBS_PORT_u, ADC_SW_TRIGGER_u, ADC_TEMP_SENSOR_EN_u, ADC_TIMER_CONVERSION_u, ADC_TIMER_SAMPLE_u, ADC_TIMER_START_u, ADC_WINDOW_COMP_u, BOOTLOADER_BCR_CFG0_u, BOOTLOADER_BCR_CFG1_u, BOOTLOADER_BCR_CFG2_u, BOOTLOADER_BCR_CONFIG_ID_u, BOOTLOADER_BCR_CRCCFG0_u, BOOTLOADER_BCR_CRCCFG1_u, BOOTLOADER_BCR_CRCCFG2_u, BOOTLOADER_BCR_CRCCFG3_u, BOOTLOADER_BCR_FLASH_WP_u, BOOTLOADER_BSL_CONFIG_ID_u, BOOTLOADER_BSL_I2C_CFG_u, BOOTLOADER_BSL_PWD_u, BOOTLOADER_BSL_UART_CFG0_u, BOOTLOADER_BSL_UART_CFG1_u, COMP_CLK_CTRL_u, COMP_CTRL0_u, COMP_DESC_u, COMP_EVENT_EN_u, COMP_INPUT_CTRL0_u, COMP_INPUT_CTRL1_u, COMP_INTR_EN_u, COMP_INTR_EVENT_u, COMP_INTR_NMI_EN_u, COMP_INTR_STS_u, COMP_INTR_SW_SET_u, COMP_OUT_CTRL0_u, COMP_OUT_CTRL1_u, COMP_PWR_EN_u, COMP_REF_CTRL0_u, COMP_REF_CTRL1_u, COMP_RST_CTRL_u, COMP_RST_STS_u, COMP_SPARE_CTRL_u, COMP_SPARE_STS_u, COMP_STS_u, CRC_CRCCONFIG_u, CRC_CRCINPUT_u, CRC_CRCRESULT_u, CRC_CRCSEED_u, CRC_PWR_EN_u, CRC_RST_CTRL_u, CRC_RST_STS_u, DAC_CAL_CTRL_u, DAC_CAL_STS_u, DAC_CLK_CTRL_u, DAC_CTRL0_u, DAC_CTRL1_u, DAC_CTRL2_u, DAC_CTRL3_u, DAC_DATA_u, DAC_DESC_u, DAC_EVENT_CTRL_u, DAC_EVENT_EN_u, DAC_INTR_EN_u, DAC_INTR_EVENT_u, DAC_INTR_NMI_EN_u, DAC_INTR_STS_u, DAC_INTR_SW_SET_u, DAC_PWR_EN_u, DAC_RST_CTRL_u, DAC_RST_STS_u, DAC_SPARE_CTRL_u, DAC_SPARE_STS_u, DMA_ARBITRATION_MASK_u, DMA_ARBITRATION_u, DMA_CFG_0_u, DMA_CFG_1_u, DMA_CFG_2_u, DMA_CLK_CTRL_u, DMA_DBG_CTRL_u, DMA_DESC_u, DMA_EARLY_IRQ_0_u, DMA_EARLY_IRQ_10_u, DMA_EARLY_IRQ_11_u, DMA_EARLY_IRQ_12_u, DMA_EARLY_IRQ_13_u, DMA_EARLY_IRQ_14_u, DMA_EARLY_IRQ_15_u, DMA_EARLY_IRQ_1_u, DMA_EARLY_IRQ_2_u, DMA_EARLY_IRQ_3_u, DMA_EARLY_IRQ_4_u, DMA_EARLY_IRQ_5_u, DMA_EARLY_IRQ_6_u, DMA_EARLY_IRQ_7_u, DMA_EARLY_IRQ_8_u, DMA_EARLY_IRQ_9_u, DMA_EARLY_IRQ_CFG_u, DMA_EVENT_EN_0_u, DMA_EVENT_EN_1_u, DMA_FILL_MODE_CFG_u, DMA_FILL_MODE_u, DMA_INTR_EN_0_u, DMA_INTR_EN_1_u, DMA_INTR_EVENT_u, DMA_INTR_NMI_EN_0_u, DMA_INTR_NMI_EN_1_u, DMA_INTR_STS_u, DMA_INTR_SW_SET_u, DMA_PWR_EN_u, DMA_REPEATED_TRANSFER_ALTERNATE_SEL_u, DMA_REPEATED_TRANSFER_CHNL_0_u, DMA_REPEATED_TRANSFER_CHNL_10_u, DMA_REPEATED_TRANSFER_CHNL_11_u, DMA_REPEATED_TRANSFER_CHNL_12_u, DMA_REPEATED_TRANSFER_CHNL_13_u, DMA_REPEATED_TRANSFER_CHNL_14_u, DMA_REPEATED_TRANSFER_CHNL_15_u, DMA_REPEATED_TRANSFER_CHNL_1_u, DMA_REPEATED_TRANSFER_CHNL_2_u, DMA_REPEATED_TRANSFER_CHNL_3_u, DMA_REPEATED_TRANSFER_CHNL_4_u, DMA_REPEATED_TRANSFER_CHNL_5_u, DMA_REPEATED_TRANSFER_CHNL_6_u, DMA_REPEATED_TRANSFER_CHNL_7_u, DMA_REPEATED_TRANSFER_CHNL_8_u, DMA_REPEATED_TRANSFER_CHNL_9_u, DMA_REPEATED_TRANSFER_EN_u, DMA_RST_CTRL_u, DMA_RST_STS_u, DMA_STRIDE_MODE_CFG_0_u, DMA_STRIDE_MODE_CFG_1_u, DMA_STRIDE_MODE_CFG_2_u, DMA_STRIDE_MODE_u, DMA_WAITONREQ_u, EVENT_FABRIC_CLK_CTRL_u, EVENT_FABRIC_DESC_u, EVENT_FABRIC_DMA_PUB_u, EVENT_FABRIC_GEN_PUB_u, EVENT_FABRIC_GEN_SUB_u, EVENT_FABRIC_PWR_EN_u, EVENT_FABRIC_RST_CTRL_u, EVENT_FABRIC_RST_STS_u, FLASH_CLK_CTRL_u, FLASH_CTRL_u, FLASH_DESC_u, FLASH_ECED_STATUS_u, FLASH_HSIZE_CTRL_u, FLASH_STATUS_u, FLASH_STS_u, FLASH_TIME_CTRL_1_u, FLASH_TIME_CTRL_2_u, FLASH_TIME_CTRL_u, FLASH_TIME_UPTD_u, GPIO_CLK_CTRL_u, GPIO_DESC_u, GPIO_DIN_11_8_u, GPIO_DIN_15_12_u, GPIO_DIN_19_16_u, GPIO_DIN_23_20_u, GPIO_DIN_27_24_u, GPIO_DIN_31_28_u, GPIO_DIN_3_0_u, GPIO_DIN_7_4_u, GPIO_DIN_u, GPIO_DMA_WR_MASK_u, GPIO_DOUT_11_8_u, GPIO_DOUT_15_12_u, GPIO_DOUT_19_16_u, GPIO_DOUT_23_20_u, GPIO_DOUT_27_24_u, GPIO_DOUT_31_28_u, GPIO_DOUT_3_0_u, GPIO_DOUT_7_4_u, GPIO_DOUT_CLR_u, GPIO_DOUT_EN_CLR_u, GPIO_DOUT_EN_SET_u, GPIO_DOUT_EN_u, GPIO_DOUT_SET_u, GPIO_DOUT_TGL_u, GPIO_DOUT_u, GPIO_EVENT_EN0_u, GPIO_EVENT_EN1_u, GPIO_FILT_EN_0_u, GPIO_FILT_EN_1_u, GPIO_INTR_EN0_u, GPIO_INTR_EN1_u, GPIO_INTR_EVENT_u, GPIO_INTR_NMI_EN0_u, GPIO_INTR_NMI_EN1_u, GPIO_INTR_POL_0_u, GPIO_INTR_POL_1_u, GPIO_INTR_STS_u, GPIO_INTR_SW_SET_u, GPIO_PWR_EN_u, GPIO_RST_CTRL_u, GPIO_RST_STS_u, GPIO_SUB_CFG_u, I2C_CLK_CTRL_u, I2C_CRC_OUT_BYTE_u, I2C_DBG_CTRL_u, I2C_DESC_u, I2C_FIFO_CTRL_u, I2C_FIFO_STS_u, I2C_FSM_STATUS_u, I2C_GLITCH_FILTER_CFG_u, I2C_INTR_EN_0_u, I2C_INTR_EN_1_u, I2C_INTR_EVENT_u, I2C_INTR_NMI_EN_0_u, I2C_INTR_NMI_EN_1_u, I2C_INTR_STS_u, I2C_INTR_SW_SET_0_u, I2C_INTR_SW_SET_1_u, I2C_MASTER_ACK_VAL_u, I2C_MASTER_CFG_u, I2C_MASTER_CLKSTRETCH_CNT_u, I2C_MASTER_CTRL_u, I2C_MASTER_MON_u, I2C_MASTER_SCL_GEN_u, I2C_MASTER_STS_u, I2C_MASTER_TIMING_CONSTRAINT_u, I2C_PEC_CTRL_u, I2C_PEC_STS_u, I2C_PWR_EN_u, I2C_RST_CTRL_u, I2C_RST_STS_u, I2C_RX_DMA_EVENT_EN_0_u, I2C_RX_DMA_EVENT_EN_1_u, I2C_RXDATA_u, I2C_SLAVE_ACK_CFG_u, I2C_SLAVE_ADDR_u, I2C_SLAVE_BYTE_ACK_u, I2C_SLAVE_CLKSTRETCH_CNT_u, I2C_SLAVE_CTRL_u, I2C_SLAVE_STS_u, I2C_SMBUS_TIMEOUT_CNT_u, I2C_SPARE_CTRL_u, I2C_SPARE_STS_u, I2C_TX_DMA_EVENT_EN_0_u, I2C_TX_DMA_EVENT_EN_1_u, I2C_TXDATA_u, IOMUX_DUMMY_u, IOMUX_PA_u, MCU_CTRL_AHB_HCLK_CTRL_u, MCU_CTRL_ANA_CLK_EN_u, MCU_CTRL_ANA_SPARE_OUT0_u, MCU_CTRL_ANA_SPARE_OUT1_u, MCU_CTRL_ANA_SPARE_STS_u, MCU_CTRL_AON_CTRL_u, MCU_CTRL_APB_PCLK_CTRL_u, MCU_CTRL_BLOCK_CLK_REQ_u, MCU_CTRL_BOOT_CFG_u, MCU_CTRL_BOR_MODE_SEL_u, MCU_CTRL_CLK_4MHZ_CTRL_u, MCU_CTRL_CLK_CTRL_u, MCU_CTRL_CLK_PWR_EN_u, MCU_CTRL_DESC_u, MCU_CTRL_GPAMPCTL_u, MCU_CTRL_GPAMPSTS_u, MCU_CTRL_HF_CLK_CTRL_u, MCU_CTRL_HF_OSC_CLK_CTRL_u, MCU_CTRL_INTR_EN_u, MCU_CTRL_INTR_EVENT_u, MCU_CTRL_LF_CLK_CTRL_u, MCU_CTRL_MCU_SW_RST_u, MCU_CTRL_PLL_CTRL1_u, MCU_CTRL_PLL_CTRL2_u, MCU_CTRL_PLL_EN_u, MCU_CTRL_PMODE_CFG_u, MCU_CTRL_PROCMONCTL_u, MCU_CTRL_PWR_SM_OVRD_CTL_u, MCU_CTRL_RST_CTRL_u, MCU_CTRL_RST_STS_u, MCU_CTRL_SPARE_CTRL_u, MCU_CTRL_SPARE_STS_u, MCU_CTRL_XO_CFG_STS_u, OPAMP_CTRL0_u, OPAMP_DESC_u, OPAMP_GAIN_CTRL0_u, OPAMP_INPUT_CTRL0_u, OPAMP_PWR_EN_u, OPAMP_RST_CTRL_u, OPAMP_RST_STS_u, OPAMP_SPARE_CTRL_u, OPAMP_SPARE_STS_u, OTP_OTP_CTRL_u, OTP_OTP_EN_u, OTP_OTP_RD_EN_u, OTP_OTP_RD_STATUS_u, OTP_OTP_STATUS_u, OTP_OTP_u, OTP_STS_u, OTP_TIMER_CTRL_u, PL230_ALT_CTRL_BASE_PTR_u, PL230_CHNL_ENABLE_CLR_u, PL230_CHNL_ENABLE_SET_u, PL230_CHNL_PRI_ALT_CLR_u, PL230_CHNL_PRI_ALT_SET_u, PL230_CHNL_PRIORITY_CLR_u, PL230_CHNL_PRIORITY_SET_u, PL230_CHNL_REQ_MASK_CLR_u, PL230_CHNL_REQ_MASK_SET_u, PL230_CHNL_SW_REQUEST_u, PL230_CHNL_USEBURST_CLR_u, PL230_CHNL_USEBURST_SET_u, PL230_CTRL_BASE_PTR_u, PL230_DMA_CFG_u, PL230_DMA_STATUS_u, PL230_DMA_WAITONREQ_STATUS_u, PL230_ERR_CLR_u, RTC_A0_DAY_u, RTC_A0_HOUR_u, RTC_A0_MIN_u, RTC_A1_DAY_u, RTC_A1_HOUR_u, RTC_A1_MIN_u, RTC_BUS_CLK_FORCE_u, RTC_CLK_CTRL_u, RTC_DEBUG_CTL_u, RTC_DESC_u, RTC_DOM_CTL_u, RTC_DOW_CTL_u, RTC_EVENT_EN_u, RTC_HR_CTL_u, RTC_INTERVAL_INTR_SEL_u, RTC_INTR_EN_u, RTC_INTR_EVENT_u, RTC_INTR_NMI_EN_u, RTC_INTR_STS_u, RTC_INTR_SW_SET_u, RTC_MIN_CTL_u, RTC_MON_CTL_u, RTC_PRD_INTR_SEL0_u, RTC_PRD_INTR_SEL1_u, RTC_PWR_EN_u, RTC_RST_CTRL_u, RTC_RST_STS_u, RTC_RTC_CAL_u, RTC_RTC_CTL_u, RTC_RTC_TEMP_CMP_u, RTC_SEC_CTL_u, RTC_YEAR_CTL_u, SPI_CLK_CTRL_u, SPI_CLK_DIV_u, SPI_CLKSEL_u, SPI_CMD_DATA_CTRL_u, SPI_CS_CTRL_u, SPI_CS_SETUP_HOLD_CNT_u, SPI_DATAFRAME_CTRL_u, SPI_DBG_CTRL_u, SPI_DESC_u, SPI_DSPI_CTRL_u, SPI_INT_FIFO_LVL_SEL_u, SPI_INTR_EN_u, SPI_INTR_EVENT_u, SPI_INTR_NMI_u, SPI_INTR_RX_DMA_EN_u, SPI_INTR_STS_u, SPI_INTR_SW_SET_u, SPI_INTR_TX_DMA_EN_u, SPI_LOOPBACK_CTRL_u, SPI_MODE_CTRL_u, SPI_MOT_MOD_CNTRL_u, SPI_PARITY_CTRL_u, SPI_PWR_EN_u, SPI_QSPI_CTRL_u, SPI_RST_CTRL_u, SPI_RST_STS_u, SPI_RX_CTRL_u, SPI_RX_FIFO_u, SPI_SCLK_CTRL_u, SPI_SPARE_CTRL_u, SPI_SPARE_STS_u, SPI_STS_u, SPI_TX_CTRL_u, SPI_TX_FIFO_u, TIMER_CC0_CAPTURE_CTRL_u, TIMER_CC0_CC_PWM_CFG_u, TIMER_CC0_CMN_CTRL_u, TIMER_CC0_COMPARE_CTRL_u, TIMER_CC0_OUTPUT_CTL_u, TIMER_CC0_SW_FORCE_u, TIMER_CC1_CAPTURE_CTRL_u, TIMER_CC1_CC_PWM_CFG_u, TIMER_CC1_CMN_CTRL_u, TIMER_CC1_COMPARE_CTRL_u, TIMER_CC1_OUTPUT_CTL_u, TIMER_CC1_SW_FORCE_u, TIMER_CC2_CAPTURE_CTRL_u, TIMER_CC2_CC_PWM_CFG_u, TIMER_CC2_CMN_CTRL_u, TIMER_CC2_COMPARE_CTRL_u, TIMER_CC2_OUTPUT_CTL_u, TIMER_CC2_SW_FORCE_u, TIMER_CC3_CAPTURE_CTRL_u, TIMER_CC3_CC_PWM_CFG_u, TIMER_CC3_CMN_CTRL_u, TIMER_CC3_COMPARE_CTRL_u, TIMER_CC3_OUTPUT_CTL_u, TIMER_CC3_SW_FORCE_u, TIMER_CC4_CMN_CTRL_u, TIMER_CC4_COMPARE_CTRL_u, TIMER_CC5_CMN_CTRL_u, TIMER_CC5_COMPARE_CTRL_u, TIMER_CLK_CONFIG_u, TIMER_CLK_CTRL_u, TIMER_CTR_CTL_u, TIMER_CTR_LOAD_VAL_u, TIMER_CTR_PL_VAL_u, TIMER_CTR_VAL_u, TIMER_DEADBAND_CFG_u, TIMER_DEBUG_CTRL_u, TIMER_DESC_u, TIMER_EVENT_CTRL_u, TIMER_EVENT_EN_0_0_u, TIMER_EVENT_EN_0_1_u, TIMER_EVENT_EN_1_0_u, TIMER_EVENT_EN_1_1_u, TIMER_FAULT_IN_CTL_u, TIMER_FAULT_SRC_CTL_u, TIMER_INPUT_CC_0_u, TIMER_INPUT_CC_1_u, TIMER_INPUT_CC_2_u, TIMER_INPUT_CC_3_u, TIMER_INPUT_FILTER_CC_0_u, TIMER_INPUT_FILTER_CC_1_u, TIMER_INPUT_FILTER_CC_2_u, TIMER_INPUT_FILTER_CC_3_u, TIMER_INTR_EN_0_u, TIMER_INTR_EN_1_u, TIMER_INTR_EVENT_u, TIMER_INTR_NMI_EN_0_u, TIMER_INTR_NMI_EN_1_u, TIMER_INTR_STS_u, TIMER_INTR_SW_SET_u, TIMER_PWR_EN_u, TIMER_QEI_DIR_u, TIMER_RCTR_LOAD_VAL_u, TIMER_RCTR_VAL_u, TIMER_RST_CTRL_u, TIMER_RST_STS_u, TIMER_TIMG_NUM_INPUT2_CC0_CAPTURE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_u, TIMER_TIMG_NUM_INPUT2_CC0_CMN_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC0_COMPARE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC0_OUTPUT_CTL_u, TIMER_TIMG_NUM_INPUT2_CC0_SW_FORCE_u, TIMER_TIMG_NUM_INPUT2_CC1_CAPTURE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_u, TIMER_TIMG_NUM_INPUT2_CC1_CMN_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC1_COMPARE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC1_OUTPUT_CTL_u, TIMER_TIMG_NUM_INPUT2_CC1_SW_FORCE_u, TIMER_TIMG_NUM_INPUT2_CLK_CONFIG_u, TIMER_TIMG_NUM_INPUT2_CLK_CTRL_u, TIMER_TIMG_NUM_INPUT2_CTR_CTL_u, TIMER_TIMG_NUM_INPUT2_CTR_LOAD_VAL_u, TIMER_TIMG_NUM_INPUT2_CTR_VAL_u, TIMER_TIMG_NUM_INPUT2_DEBUG_CTRL_u, TIMER_TIMG_NUM_INPUT2_DESC_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_1_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_1_u, TIMER_TIMG_NUM_INPUT2_INPUT_CC_0_u, TIMER_TIMG_NUM_INPUT2_INPUT_CC_1_u, TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_0_u, TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_1_u, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_u, TIMER_TIMG_NUM_INPUT2_INTR_EN_1_u, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_u, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_u, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_1_u, TIMER_TIMG_NUM_INPUT2_INTR_STS_u, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_u, TIMER_TIMG_NUM_INPUT2_PWR_EN_u, TIMER_TIMG_NUM_INPUT2_RST_CTRL_u, TIMER_TIMG_NUM_INPUT2_RST_STS_u, TIMER_TIMG_NUM_INPUT2_TRIG_IN_u, TIMER_TIMG_NUM_INPUT2_TRIG_OUT_u, TIMER_TRIG_IN_u, TIMER_TRIG_OUT_u, UART_ADDR_u, UART_ADDRMASK_u, UART_BRDDEN_u, UART_BRDNUM_u, UART_CFG_u, UART_CLK_CTRL_u, UART_CLK_DIV_u, UART_CLK_SEL_u, UART_CLKCFG_u, UART_CTRL_u, UART_DBG_CTRL_u, UART_DESC_u, UART_DMA_RX_EVENT_EN0_u, UART_DMA_RX_EVENT_EN1_u, UART_DMA_TX_EVENT_EN0_u, UART_DMA_TX_EVENT_EN1_u, UART_FIFOLS_u, UART_FIFOSTS_u, UART_FSM_STS_u, UART_GFCTL_u, UART_INTR_EN0_u, UART_INTR_EN1_u, UART_INTR_EVENT_u, UART_INTR_NMI_EN0_u, UART_INTR_NMI_EN1_u, UART_INTR_STS_u, UART_INTR_SW_SET_u, UART_PWR_EN_u, UART_RST_CTRL_u, UART_RST_STS_u, UART_RXDATA_u, UART_STS_u, UART_TXDATA_u, VREF_CLK_CTRL_u, VREF_CTRL_u, VREF_DESC_u, VREF_PWR_EN_u, VREF_RST_CTRL_u, VREF_RST_STS_u, VREF_SH_CTRL_u, VREF_SPARE_CTRL_u, VREF_SPARE_STS_u, VREF_STS_u, VULTAN_FLASH_ADDR_u, VULTAN_FLASH_CTRL_u, VULTAN_FLASH_DATA0_u, VULTAN_FLASH_DATA1_u, VULTAN_FLASH_DATA2_u, VULTAN_FLASH_DATA3_u, VULTAN_FLASH_IRQ_ENABLE_CLR_u, VULTAN_FLASH_IRQ_ENABLE_SET_u, VULTAN_FLASH_IRQ_MASKED_STATUS_u, VULTAN_FLASH_IRQ_STATUS_CLR_u, VULTAN_FLASH_IRQ_STATUS_SET_u, VULTAN_FLASH_STATUS_u, WATCHDOG_DESC_u, WATCHDOG_EVENT_EN_u, WATCHDOG_HALT_MODE_u, WATCHDOG_INTR_EN_u, WATCHDOG_INTR_EVENT_u, WATCHDOG_INTR_NMI_EN_u, WATCHDOG_INTR_STS_u, WATCHDOG_INTR_SW_SET_u, WATCHDOG_PWR_EN_u, WATCHDOG_RST_CTRL_u, WATCHDOG_RST_STS_u, WATCHDOG_WWDT_CTL0_u, WATCHDOG_WWDT_CTL1_u, WATCHDOG_WWDT_EN_u, WATCHDOG_WWDT_RESTART_u, WATCHDOG_WWDT_STS_u
packed_w : ADC_BLOCK_ASYNC_REQ_u, ADC_CALIBRATION_REQ_u, ADC_CHNL_CFG_u, ADC_CLK_CTRL_u, ADC_CLK_SEL_u, ADC_CONV_CFG_u, ADC_DBG_CTRL_u, ADC_DESC_u, ADC_DMA_EVENT_EN_0_u, ADC_DMA_EVENT_EN_1_u, ADC_DMA_REG_u, ADC_DMA_TRANSFER_CNT_u, ADC_EOC_ANA_u, ADC_EVENT_EN_0_u, ADC_EVENT_EN_1_u, ADC_HW_AVG_CFG_u, ADC_INTR_EN_0_u, ADC_INTR_EN_1_u, ADC_INTR_EVENT_u, ADC_INTR_NMI_EN_0_u, ADC_INTR_NMI_EN_1_u, ADC_INTR_STS_u, ADC_INTR_SW_u, ADC_POWER_DN_u, ADC_PUBS_PORT_u, ADC_PWR_EN_u, ADC_RESULT_CFG_u, ADC_RESULT_u, ADC_RST_CTRL_u, ADC_RST_STS_u, ADC_SM_STATE_u, ADC_SPARE_CTRL_u, ADC_SPARE_STS_u, ADC_STATUS_u, ADC_SUBS_PORT_u, ADC_SW_TRIGGER_u, ADC_TEMP_SENSOR_EN_u, ADC_TIMER_CONVERSION_u, ADC_TIMER_SAMPLE_u, ADC_TIMER_START_u, ADC_WINDOW_COMP_u, BOOTLOADER_BCR_CFG0_u, BOOTLOADER_BCR_CFG1_u, BOOTLOADER_BCR_CFG2_u, BOOTLOADER_BCR_CONFIG_ID_u, BOOTLOADER_BCR_CRCCFG0_u, BOOTLOADER_BCR_CRCCFG1_u, BOOTLOADER_BCR_CRCCFG2_u, BOOTLOADER_BCR_CRCCFG3_u, BOOTLOADER_BCR_FLASH_WP_u, BOOTLOADER_BSL_CONFIG_ID_u, BOOTLOADER_BSL_I2C_CFG_u, BOOTLOADER_BSL_PWD_u, BOOTLOADER_BSL_UART_CFG0_u, BOOTLOADER_BSL_UART_CFG1_u, COMP_CLK_CTRL_u, COMP_CTRL0_u, COMP_DESC_u, COMP_EVENT_EN_u, COMP_INPUT_CTRL0_u, COMP_INPUT_CTRL1_u, COMP_INTR_EN_u, COMP_INTR_EVENT_u, COMP_INTR_NMI_EN_u, COMP_INTR_STS_u, COMP_INTR_SW_SET_u, COMP_OUT_CTRL0_u, COMP_OUT_CTRL1_u, COMP_PWR_EN_u, COMP_REF_CTRL0_u, COMP_REF_CTRL1_u, COMP_RST_CTRL_u, COMP_RST_STS_u, COMP_SPARE_CTRL_u, COMP_SPARE_STS_u, COMP_STS_u, CRC_CRCCONFIG_u, CRC_CRCINPUT_u, CRC_CRCRESULT_u, CRC_CRCSEED_u, CRC_PWR_EN_u, CRC_RST_CTRL_u, CRC_RST_STS_u, DAC_CAL_CTRL_u, DAC_CAL_STS_u, DAC_CLK_CTRL_u, DAC_CTRL0_u, DAC_CTRL1_u, DAC_CTRL2_u, DAC_CTRL3_u, DAC_DATA_u, DAC_DESC_u, DAC_EVENT_CTRL_u, DAC_EVENT_EN_u, DAC_INTR_EN_u, DAC_INTR_EVENT_u, DAC_INTR_NMI_EN_u, DAC_INTR_STS_u, DAC_INTR_SW_SET_u, DAC_PWR_EN_u, DAC_RST_CTRL_u, DAC_RST_STS_u, DAC_SPARE_CTRL_u, DAC_SPARE_STS_u, DMA_ARBITRATION_MASK_u, DMA_ARBITRATION_u, DMA_CFG_0_u, DMA_CFG_1_u, DMA_CFG_2_u, DMA_CLK_CTRL_u, DMA_DBG_CTRL_u, DMA_DESC_u, DMA_EARLY_IRQ_0_u, DMA_EARLY_IRQ_10_u, DMA_EARLY_IRQ_11_u, DMA_EARLY_IRQ_12_u, DMA_EARLY_IRQ_13_u, DMA_EARLY_IRQ_14_u, DMA_EARLY_IRQ_15_u, DMA_EARLY_IRQ_1_u, DMA_EARLY_IRQ_2_u, DMA_EARLY_IRQ_3_u, DMA_EARLY_IRQ_4_u, DMA_EARLY_IRQ_5_u, DMA_EARLY_IRQ_6_u, DMA_EARLY_IRQ_7_u, DMA_EARLY_IRQ_8_u, DMA_EARLY_IRQ_9_u, DMA_EARLY_IRQ_CFG_u, DMA_EVENT_EN_0_u, DMA_EVENT_EN_1_u, DMA_FILL_MODE_CFG_u, DMA_FILL_MODE_u, DMA_INTR_EN_0_u, DMA_INTR_EN_1_u, DMA_INTR_EVENT_u, DMA_INTR_NMI_EN_0_u, DMA_INTR_NMI_EN_1_u, DMA_INTR_STS_u, DMA_INTR_SW_SET_u, DMA_PWR_EN_u, DMA_REPEATED_TRANSFER_ALTERNATE_SEL_u, DMA_REPEATED_TRANSFER_CHNL_0_u, DMA_REPEATED_TRANSFER_CHNL_10_u, DMA_REPEATED_TRANSFER_CHNL_11_u, DMA_REPEATED_TRANSFER_CHNL_12_u, DMA_REPEATED_TRANSFER_CHNL_13_u, DMA_REPEATED_TRANSFER_CHNL_14_u, DMA_REPEATED_TRANSFER_CHNL_15_u, DMA_REPEATED_TRANSFER_CHNL_1_u, DMA_REPEATED_TRANSFER_CHNL_2_u, DMA_REPEATED_TRANSFER_CHNL_3_u, DMA_REPEATED_TRANSFER_CHNL_4_u, DMA_REPEATED_TRANSFER_CHNL_5_u, DMA_REPEATED_TRANSFER_CHNL_6_u, DMA_REPEATED_TRANSFER_CHNL_7_u, DMA_REPEATED_TRANSFER_CHNL_8_u, DMA_REPEATED_TRANSFER_CHNL_9_u, DMA_REPEATED_TRANSFER_EN_u, DMA_RST_CTRL_u, DMA_RST_STS_u, DMA_STRIDE_MODE_CFG_0_u, DMA_STRIDE_MODE_CFG_1_u, DMA_STRIDE_MODE_CFG_2_u, DMA_STRIDE_MODE_u, DMA_WAITONREQ_u, EVENT_FABRIC_CLK_CTRL_u, EVENT_FABRIC_DESC_u, EVENT_FABRIC_DMA_PUB_u, EVENT_FABRIC_GEN_PUB_u, EVENT_FABRIC_GEN_SUB_u, EVENT_FABRIC_PWR_EN_u, EVENT_FABRIC_RST_CTRL_u, EVENT_FABRIC_RST_STS_u, FLASH_CLK_CTRL_u, FLASH_CTRL_u, FLASH_DESC_u, FLASH_ECED_STATUS_u, FLASH_HSIZE_CTRL_u, FLASH_STATUS_u, FLASH_STS_u, FLASH_TIME_CTRL_1_u, FLASH_TIME_CTRL_2_u, FLASH_TIME_CTRL_u, FLASH_TIME_UPTD_u, GPIO_CLK_CTRL_u, GPIO_DESC_u, GPIO_DIN_11_8_u, GPIO_DIN_15_12_u, GPIO_DIN_19_16_u, GPIO_DIN_23_20_u, GPIO_DIN_27_24_u, GPIO_DIN_31_28_u, GPIO_DIN_3_0_u, GPIO_DIN_7_4_u, GPIO_DIN_u, GPIO_DMA_WR_MASK_u, GPIO_DOUT_11_8_u, GPIO_DOUT_15_12_u, GPIO_DOUT_19_16_u, GPIO_DOUT_23_20_u, GPIO_DOUT_27_24_u, GPIO_DOUT_31_28_u, GPIO_DOUT_3_0_u, GPIO_DOUT_7_4_u, GPIO_DOUT_CLR_u, GPIO_DOUT_EN_CLR_u, GPIO_DOUT_EN_SET_u, GPIO_DOUT_EN_u, GPIO_DOUT_SET_u, GPIO_DOUT_TGL_u, GPIO_DOUT_u, GPIO_EVENT_EN0_u, GPIO_EVENT_EN1_u, GPIO_FILT_EN_0_u, GPIO_FILT_EN_1_u, GPIO_INTR_EN0_u, GPIO_INTR_EN1_u, GPIO_INTR_EVENT_u, GPIO_INTR_NMI_EN0_u, GPIO_INTR_NMI_EN1_u, GPIO_INTR_POL_0_u, GPIO_INTR_POL_1_u, GPIO_INTR_STS_u, GPIO_INTR_SW_SET_u, GPIO_PWR_EN_u, GPIO_RST_CTRL_u, GPIO_RST_STS_u, GPIO_SUB_CFG_u, I2C_CLK_CTRL_u, I2C_CRC_OUT_BYTE_u, I2C_DBG_CTRL_u, I2C_DESC_u, I2C_FIFO_CTRL_u, I2C_FIFO_STS_u, I2C_FSM_STATUS_u, I2C_GLITCH_FILTER_CFG_u, I2C_INTR_EN_0_u, I2C_INTR_EN_1_u, I2C_INTR_EVENT_u, I2C_INTR_NMI_EN_0_u, I2C_INTR_NMI_EN_1_u, I2C_INTR_STS_u, I2C_INTR_SW_SET_0_u, I2C_INTR_SW_SET_1_u, I2C_MASTER_ACK_VAL_u, I2C_MASTER_CFG_u, I2C_MASTER_CLKSTRETCH_CNT_u, I2C_MASTER_CTRL_u, I2C_MASTER_MON_u, I2C_MASTER_SCL_GEN_u, I2C_MASTER_STS_u, I2C_MASTER_TIMING_CONSTRAINT_u, I2C_PEC_CTRL_u, I2C_PEC_STS_u, I2C_PWR_EN_u, I2C_RST_CTRL_u, I2C_RST_STS_u, I2C_RX_DMA_EVENT_EN_0_u, I2C_RX_DMA_EVENT_EN_1_u, I2C_RXDATA_u, I2C_SLAVE_ACK_CFG_u, I2C_SLAVE_ADDR_u, I2C_SLAVE_BYTE_ACK_u, I2C_SLAVE_CLKSTRETCH_CNT_u, I2C_SLAVE_CTRL_u, I2C_SLAVE_STS_u, I2C_SMBUS_TIMEOUT_CNT_u, I2C_SPARE_CTRL_u, I2C_SPARE_STS_u, I2C_TX_DMA_EVENT_EN_0_u, I2C_TX_DMA_EVENT_EN_1_u, I2C_TXDATA_u, IOMUX_DUMMY_u, IOMUX_PA_u, MCU_CTRL_AHB_HCLK_CTRL_u, MCU_CTRL_ANA_CLK_EN_u, MCU_CTRL_ANA_SPARE_OUT0_u, MCU_CTRL_ANA_SPARE_OUT1_u, MCU_CTRL_ANA_SPARE_STS_u, MCU_CTRL_AON_CTRL_u, MCU_CTRL_APB_PCLK_CTRL_u, MCU_CTRL_BLOCK_CLK_REQ_u, MCU_CTRL_BOOT_CFG_u, MCU_CTRL_BOR_MODE_SEL_u, MCU_CTRL_CLK_4MHZ_CTRL_u, MCU_CTRL_CLK_CTRL_u, MCU_CTRL_CLK_PWR_EN_u, MCU_CTRL_DESC_u, MCU_CTRL_GPAMPCTL_u, MCU_CTRL_GPAMPSTS_u, MCU_CTRL_HF_CLK_CTRL_u, MCU_CTRL_HF_OSC_CLK_CTRL_u, MCU_CTRL_INTR_EN_u, MCU_CTRL_INTR_EVENT_u, MCU_CTRL_LF_CLK_CTRL_u, MCU_CTRL_MCU_SW_RST_u, MCU_CTRL_PLL_CTRL1_u, MCU_CTRL_PLL_CTRL2_u, MCU_CTRL_PLL_EN_u, MCU_CTRL_PMODE_CFG_u, MCU_CTRL_PROCMONCTL_u, MCU_CTRL_PWR_SM_OVRD_CTL_u, MCU_CTRL_RST_CTRL_u, MCU_CTRL_RST_STS_u, MCU_CTRL_SPARE_CTRL_u, MCU_CTRL_SPARE_STS_u, MCU_CTRL_XO_CFG_STS_u, OPAMP_CTRL0_u, OPAMP_DESC_u, OPAMP_GAIN_CTRL0_u, OPAMP_INPUT_CTRL0_u, OPAMP_PWR_EN_u, OPAMP_RST_CTRL_u, OPAMP_RST_STS_u, OPAMP_SPARE_CTRL_u, OPAMP_SPARE_STS_u, OTP_OTP_CTRL_u, OTP_OTP_EN_u, OTP_OTP_RD_EN_u, OTP_OTP_RD_STATUS_u, OTP_OTP_STATUS_u, OTP_OTP_u, OTP_STS_u, OTP_TIMER_CTRL_u, PL230_ALT_CTRL_BASE_PTR_u, PL230_CHNL_ENABLE_CLR_u, PL230_CHNL_ENABLE_SET_u, PL230_CHNL_PRI_ALT_CLR_u, PL230_CHNL_PRI_ALT_SET_u, PL230_CHNL_PRIORITY_CLR_u, PL230_CHNL_PRIORITY_SET_u, PL230_CHNL_REQ_MASK_CLR_u, PL230_CHNL_REQ_MASK_SET_u, PL230_CHNL_SW_REQUEST_u, PL230_CHNL_USEBURST_CLR_u, PL230_CHNL_USEBURST_SET_u, PL230_CTRL_BASE_PTR_u, PL230_DMA_CFG_u, PL230_DMA_STATUS_u, PL230_DMA_WAITONREQ_STATUS_u, PL230_ERR_CLR_u, RTC_A0_DAY_u, RTC_A0_HOUR_u, RTC_A0_MIN_u, RTC_A1_DAY_u, RTC_A1_HOUR_u, RTC_A1_MIN_u, RTC_BUS_CLK_FORCE_u, RTC_CLK_CTRL_u, RTC_DEBUG_CTL_u, RTC_DESC_u, RTC_DOM_CTL_u, RTC_DOW_CTL_u, RTC_EVENT_EN_u, RTC_HR_CTL_u, RTC_INTERVAL_INTR_SEL_u, RTC_INTR_EN_u, RTC_INTR_EVENT_u, RTC_INTR_NMI_EN_u, RTC_INTR_STS_u, RTC_INTR_SW_SET_u, RTC_MIN_CTL_u, RTC_MON_CTL_u, RTC_PRD_INTR_SEL0_u, RTC_PRD_INTR_SEL1_u, RTC_PWR_EN_u, RTC_RST_CTRL_u, RTC_RST_STS_u, RTC_RTC_CAL_u, RTC_RTC_CTL_u, RTC_RTC_TEMP_CMP_u, RTC_SEC_CTL_u, RTC_YEAR_CTL_u, SPI_CLK_CTRL_u, SPI_CLK_DIV_u, SPI_CLKSEL_u, SPI_CMD_DATA_CTRL_u, SPI_CS_CTRL_u, SPI_CS_SETUP_HOLD_CNT_u, SPI_DATAFRAME_CTRL_u, SPI_DBG_CTRL_u, SPI_DESC_u, SPI_DSPI_CTRL_u, SPI_INT_FIFO_LVL_SEL_u, SPI_INTR_EN_u, SPI_INTR_EVENT_u, SPI_INTR_NMI_u, SPI_INTR_RX_DMA_EN_u, SPI_INTR_STS_u, SPI_INTR_SW_SET_u, SPI_INTR_TX_DMA_EN_u, SPI_LOOPBACK_CTRL_u, SPI_MODE_CTRL_u, SPI_MOT_MOD_CNTRL_u, SPI_PARITY_CTRL_u, SPI_PWR_EN_u, SPI_QSPI_CTRL_u, SPI_RST_CTRL_u, SPI_RST_STS_u, SPI_RX_CTRL_u, SPI_RX_FIFO_u, SPI_SCLK_CTRL_u, SPI_SPARE_CTRL_u, SPI_SPARE_STS_u, SPI_STS_u, SPI_TX_CTRL_u, SPI_TX_FIFO_u, TIMER_CC0_CAPTURE_CTRL_u, TIMER_CC0_CC_PWM_CFG_u, TIMER_CC0_CMN_CTRL_u, TIMER_CC0_COMPARE_CTRL_u, TIMER_CC0_OUTPUT_CTL_u, TIMER_CC0_SW_FORCE_u, TIMER_CC1_CAPTURE_CTRL_u, TIMER_CC1_CC_PWM_CFG_u, TIMER_CC1_CMN_CTRL_u, TIMER_CC1_COMPARE_CTRL_u, TIMER_CC1_OUTPUT_CTL_u, TIMER_CC1_SW_FORCE_u, TIMER_CC2_CAPTURE_CTRL_u, TIMER_CC2_CC_PWM_CFG_u, TIMER_CC2_CMN_CTRL_u, TIMER_CC2_COMPARE_CTRL_u, TIMER_CC2_OUTPUT_CTL_u, TIMER_CC2_SW_FORCE_u, TIMER_CC3_CAPTURE_CTRL_u, TIMER_CC3_CC_PWM_CFG_u, TIMER_CC3_CMN_CTRL_u, TIMER_CC3_COMPARE_CTRL_u, TIMER_CC3_OUTPUT_CTL_u, TIMER_CC3_SW_FORCE_u, TIMER_CC4_CMN_CTRL_u, TIMER_CC4_COMPARE_CTRL_u, TIMER_CC5_CMN_CTRL_u, TIMER_CC5_COMPARE_CTRL_u, TIMER_CLK_CONFIG_u, TIMER_CLK_CTRL_u, TIMER_CTR_CTL_u, TIMER_CTR_LOAD_VAL_u, TIMER_CTR_PL_VAL_u, TIMER_CTR_VAL_u, TIMER_DEADBAND_CFG_u, TIMER_DEBUG_CTRL_u, TIMER_DESC_u, TIMER_EVENT_CTRL_u, TIMER_EVENT_EN_0_0_u, TIMER_EVENT_EN_0_1_u, TIMER_EVENT_EN_1_0_u, TIMER_EVENT_EN_1_1_u, TIMER_FAULT_IN_CTL_u, TIMER_FAULT_SRC_CTL_u, TIMER_INPUT_CC_0_u, TIMER_INPUT_CC_1_u, TIMER_INPUT_CC_2_u, TIMER_INPUT_CC_3_u, TIMER_INPUT_FILTER_CC_0_u, TIMER_INPUT_FILTER_CC_1_u, TIMER_INPUT_FILTER_CC_2_u, TIMER_INPUT_FILTER_CC_3_u, TIMER_INTR_EN_0_u, TIMER_INTR_EN_1_u, TIMER_INTR_EVENT_u, TIMER_INTR_NMI_EN_0_u, TIMER_INTR_NMI_EN_1_u, TIMER_INTR_STS_u, TIMER_INTR_SW_SET_u, TIMER_PWR_EN_u, TIMER_QEI_DIR_u, TIMER_RCTR_LOAD_VAL_u, TIMER_RCTR_VAL_u, TIMER_RST_CTRL_u, TIMER_RST_STS_u, TIMER_TIMG_NUM_INPUT2_CC0_CAPTURE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_u, TIMER_TIMG_NUM_INPUT2_CC0_CMN_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC0_COMPARE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC0_OUTPUT_CTL_u, TIMER_TIMG_NUM_INPUT2_CC0_SW_FORCE_u, TIMER_TIMG_NUM_INPUT2_CC1_CAPTURE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_u, TIMER_TIMG_NUM_INPUT2_CC1_CMN_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC1_COMPARE_CTRL_u, TIMER_TIMG_NUM_INPUT2_CC1_OUTPUT_CTL_u, TIMER_TIMG_NUM_INPUT2_CC1_SW_FORCE_u, TIMER_TIMG_NUM_INPUT2_CLK_CONFIG_u, TIMER_TIMG_NUM_INPUT2_CLK_CTRL_u, TIMER_TIMG_NUM_INPUT2_CTR_CTL_u, TIMER_TIMG_NUM_INPUT2_CTR_LOAD_VAL_u, TIMER_TIMG_NUM_INPUT2_CTR_VAL_u, TIMER_TIMG_NUM_INPUT2_DEBUG_CTRL_u, TIMER_TIMG_NUM_INPUT2_DESC_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_1_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_u, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_1_u, TIMER_TIMG_NUM_INPUT2_INPUT_CC_0_u, TIMER_TIMG_NUM_INPUT2_INPUT_CC_1_u, TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_0_u, TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_1_u, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_u, TIMER_TIMG_NUM_INPUT2_INTR_EN_1_u, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_u, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_u, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_1_u, TIMER_TIMG_NUM_INPUT2_INTR_STS_u, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_u, TIMER_TIMG_NUM_INPUT2_PWR_EN_u, TIMER_TIMG_NUM_INPUT2_RST_CTRL_u, TIMER_TIMG_NUM_INPUT2_RST_STS_u, TIMER_TIMG_NUM_INPUT2_TRIG_IN_u, TIMER_TIMG_NUM_INPUT2_TRIG_OUT_u, TIMER_TRIG_IN_u, TIMER_TRIG_OUT_u, UART_ADDR_u, UART_ADDRMASK_u, UART_BRDDEN_u, UART_BRDNUM_u, UART_CFG_u, UART_CLK_CTRL_u, UART_CLK_DIV_u, UART_CLK_SEL_u, UART_CLKCFG_u, UART_CTRL_u, UART_DBG_CTRL_u, UART_DESC_u, UART_DMA_RX_EVENT_EN0_u, UART_DMA_RX_EVENT_EN1_u, UART_DMA_TX_EVENT_EN0_u, UART_DMA_TX_EVENT_EN1_u, UART_FIFOLS_u, UART_FIFOSTS_u, UART_FSM_STS_u, UART_GFCTL_u, UART_INTR_EN0_u, UART_INTR_EN1_u, UART_INTR_EVENT_u, UART_INTR_NMI_EN0_u, UART_INTR_NMI_EN1_u, UART_INTR_STS_u, UART_INTR_SW_SET_u, UART_PWR_EN_u, UART_RST_CTRL_u, UART_RST_STS_u, UART_RXDATA_u, UART_STS_u, UART_TXDATA_u, VREF_CLK_CTRL_u, VREF_CTRL_u, VREF_DESC_u, VREF_PWR_EN_u, VREF_RST_CTRL_u, VREF_RST_STS_u, VREF_SH_CTRL_u, VREF_SPARE_CTRL_u, VREF_SPARE_STS_u, VREF_STS_u, VULTAN_FLASH_ADDR_u, VULTAN_FLASH_CTRL_u, VULTAN_FLASH_DATA0_u, VULTAN_FLASH_DATA1_u, VULTAN_FLASH_DATA2_u, VULTAN_FLASH_DATA3_u, VULTAN_FLASH_IRQ_ENABLE_CLR_u, VULTAN_FLASH_IRQ_ENABLE_SET_u, VULTAN_FLASH_IRQ_MASKED_STATUS_u, VULTAN_FLASH_IRQ_STATUS_CLR_u, VULTAN_FLASH_IRQ_STATUS_SET_u, VULTAN_FLASH_STATUS_u, WATCHDOG_DESC_u, WATCHDOG_EVENT_EN_u, WATCHDOG_HALT_MODE_u, WATCHDOG_INTR_EN_u, WATCHDOG_INTR_EVENT_u, WATCHDOG_INTR_NMI_EN_u, WATCHDOG_INTR_STS_u, WATCHDOG_INTR_SW_SET_u, WATCHDOG_PWR_EN_u, WATCHDOG_RST_CTRL_u, WATCHDOG_RST_STS_u, WATCHDOG_WWDT_CTL0_u, WATCHDOG_WWDT_CTL1_u, WATCHDOG_WWDT_EN_u, WATCHDOG_WWDT_RESTART_u, WATCHDOG_WWDT_STS_u
par_en : UART_CFG_REG_s
PARITY_CTRL : SPI_REGS_s
parity_en : spi_cfg_t, SPI_PARITY_CTRL_REG_s, uart_cfg_s
parity_err : UART_INTR_EVENT_REG_s
parity_err_en : UART_INTR_EN0_REG_s
parity_err_nmi_en : UART_INTR_NMI_EN0_REG_s
parity_err_sw_set : UART_INTR_SW_SET_REG_s
parity_error : SPI_INTR_EVENT_REG_s
parity_error_en : SPI_INTR_EN_REG_s
parity_error_nmi_en : SPI_INTR_NMI_REG_s
parity_error_rx_dma_en : SPI_INTR_RX_DMA_EN_REG_s
parity_error_sw_set : SPI_INTR_SW_SET_REG_s
parity_error_tx_dma_en : SPI_INTR_TX_DMA_EN_REG_s
partname : CoreSightPart
partnumber : CoreSightPart
pclk_div : MCU_CTRL_APB_PCLK_CTRL_REG_s
PEC_CTRL : I2C_REGS_s
pec_en : I2C_PEC_CTRL_REG_s
pec_err : I2C_INTR_EVENT_REG_s
pec_err_en : I2C_INTR_EN_0_REG_s
pec_err_nmi_en : I2C_INTR_NMI_EN_0_REG_s
pec_err_sw_set : I2C_INTR_SW_SET_0_REG_s
pec_error : I2C_PEC_STS_REG_s
PEC_STS : I2C_REGS_s
period_cnt : VREF_SH_CTRL_REG_s
peripheral_mode : SPI_MODE_CTRL_REG_s
PL230_ALT_CTRL_BASE_PTR_REG_s : PL230_ALT_CTRL_BASE_PTR_u
PL230_CHNL_ENABLE_CLR_REG_s : PL230_CHNL_ENABLE_CLR_u
PL230_CHNL_ENABLE_SET_REG_s : PL230_CHNL_ENABLE_SET_u
PL230_CHNL_PRI_ALT_CLR_REG_s : PL230_CHNL_PRI_ALT_CLR_u
PL230_CHNL_PRI_ALT_SET_REG_s : PL230_CHNL_PRI_ALT_SET_u
PL230_CHNL_PRIORITY_CLR_REG_s : PL230_CHNL_PRIORITY_CLR_u
PL230_CHNL_PRIORITY_SET_REG_s : PL230_CHNL_PRIORITY_SET_u
PL230_CHNL_REQ_MASK_CLR_REG_s : PL230_CHNL_REQ_MASK_CLR_u
PL230_CHNL_REQ_MASK_SET_REG_s : PL230_CHNL_REQ_MASK_SET_u
PL230_CHNL_SW_REQUEST_REG_s : PL230_CHNL_SW_REQUEST_u
PL230_CHNL_USEBURST_CLR_REG_s : PL230_CHNL_USEBURST_CLR_u
PL230_CHNL_USEBURST_SET_REG_s : PL230_CHNL_USEBURST_SET_u
PL230_CTRL_BASE_PTR_REG_s : PL230_CTRL_BASE_PTR_u
PL230_DMA_CFG_REG_s : PL230_DMA_CFG_u
PL230_DMA_STATUS_REG_s : PL230_DMA_STATUS_u
PL230_DMA_WAITONREQ_STATUS_REG_s : PL230_DMA_WAITONREQ_STATUS_u
PL230_ERR_CLR_REG_s : PL230_ERR_CLR_u
pl_en : TIMER_CTR_CTL_REG_s
pl_val : TIMER_CTR_PL_VAL_REG_s
pll_bw : MCU_CTRL_PLL_CTRL1_REG_s
pll_clk_en_ovrd_en : MCU_CTRL_ANA_CLK_EN_REG_s
pll_clk_en_ovrd_val : MCU_CTRL_ANA_CLK_EN_REG_s
pll_cp_icfg : MCU_CTRL_PLL_EN_REG_s
PLL_CTRL1 : MCU_CTRL_REGS_s
PLL_CTRL2 : MCU_CTRL_REGS_s
PLL_EN : MCU_CTRL_REGS_s
pll_en : MCU_CTRL_PLL_EN_REG_s
pll_freq_chng_time : MCU_CTRL_PLL_CTRL1_REG_s
pll_mdiv_clk0 : MCU_CTRL_PLL_CTRL2_REG_s
pll_mdiv_clk0_en : MCU_CTRL_PLL_EN_REG_s
pll_mdiv_clk1 : MCU_CTRL_PLL_CTRL2_REG_s
pll_mdiv_clk1_en : MCU_CTRL_PLL_EN_REG_s
pll_mdiv_clk2x : MCU_CTRL_PLL_CTRL2_REG_s
pll_mdiv_clk2x_en : MCU_CTRL_PLL_EN_REG_s
pll_pdiv : MCU_CTRL_PLL_CTRL2_REG_s
pll_pfd_width_cfg : MCU_CTRL_PLL_CTRL1_REG_s
pll_pwr_en : MCU_CTRL_CLK_PWR_EN_REG_s
pll_qdiv : MCU_CTRL_PLL_CTRL2_REG_s
pll_ref_sel : MCU_CTRL_PLL_CTRL1_REG_s
pll_sw_cg_en : MCU_CTRL_PLL_EN_REG_s
pll_vco_freq : MCU_CTRL_PLL_CTRL1_REG_s
PMODE_CFG : MCU_CTRL_REGS_s
PMUCTRL : SYSCTRL_REGS_s
poly_type : crc_cfg_s, CRC_CRCCONFIG_REG_s
POWER_DN : ADC_REGS_s
prd0 : RTC_INTR_EVENT_REG_s
prd0_en : RTC_INTR_EN_REG_s
prd0_event_en : RTC_EVENT_EN_REG_s
prd0_nmi_en : RTC_INTR_NMI_EN_REG_s
prd0_sw_set : RTC_INTR_SW_SET_REG_s
prd1 : RTC_INTR_EVENT_REG_s
prd1_en : RTC_INTR_EN_REG_s
prd1_event_en : RTC_EVENT_EN_REG_s
prd1_nmi_en : RTC_INTR_NMI_EN_REG_s
prd1_sw_set : RTC_INTR_SW_SET_REG_s
PRD_INTR_SEL0 : RTC_REGS_s
PRD_INTR_SEL1 : RTC_REGS_s
prd_intr_sel_0 : RTC_PRD_INTR_SEL0_REG_s
prd_intr_sel_1 : RTC_PRD_INTR_SEL1_REG_s
proc_mon_en : MCU_CTRL_PROCMONCTL_REG_s
proc_mon_pwr_en : MCU_CTRL_PROCMONCTL_REG_s
PROCMONCTL : MCU_CTRL_REGS_s
pub : event_fabric_chnl_cfg
PUBS_PORT : ADC_REGS_s
pubs_port : ADC_PUBS_PORT_REG_s
pull_down : IOMUX_PA_REG_s
pull_up : IOMUX_PA_REG_s
pwm_high_period : timer_pwm_cfg_t
pwm_period : timer_pwm_cfg_t
pwr_dn : ADC_POWER_DN_REG_s
PWR_EN : ADC_REGS_s, COMP_REGS_s, CRC_REGS_s, DAC_REGS_s, DMA_REGS_s, EVENT_FABRIC_REGS_s, GPIO_REGS_s, I2C_REGS_s, OPAMP_REGS_s, RTC_REGS_s, SPI_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_PWR_EN_u, TIMER_TIMG_NUM_INPUT2_REGS_s, UART_REGS_s, VREF_REGS_s, WATCHDOG_REGS_s
pwr_en : ADC_PWR_EN_REG_s, COMP_PWR_EN_REG_s, CRC_PWR_EN_REG_s, DAC_PWR_EN_REG_s, DMA_PWR_EN_REG_s, EVENT_FABRIC_PWR_EN_REG_s, GPIO_PWR_EN_REG_s, I2C_PWR_EN_REG_s, OPAMP_PWR_EN_REG_s, RTC_PWR_EN_REG_s, SPI_PWR_EN_REG_s, TIMER_PWR_EN_REG_s, TIMER_TIMG_NUM_INPUT2_PWR_EN_REG_s, UART_PWR_EN_REG_s, VREF_PWR_EN_REG_s, WATCHDOG_PWR_EN_REG_s
pwr_en_key : ADC_PWR_EN_REG_s, COMP_PWR_EN_REG_s, CRC_PWR_EN_REG_s, DAC_PWR_EN_REG_s, DMA_PWR_EN_REG_s, EVENT_FABRIC_PWR_EN_REG_s, GPIO_PWR_EN_REG_s, I2C_PWR_EN_REG_s, OPAMP_PWR_EN_REG_s, RTC_PWR_EN_REG_s, SPI_PWR_EN_REG_s, TIMER_PWR_EN_REG_s, TIMER_TIMG_NUM_INPUT2_PWR_EN_REG_s, UART_PWR_EN_REG_s, VREF_PWR_EN_REG_s, WATCHDOG_PWR_EN_REG_s
PWR_SM_OVRD_CTL : MCU_CTRL_REGS_s