Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

samp_en : comp_out_cfg_s, COMP_OUT_CTRL0_REG_s
samp_tim_en : dac_cfg_s, DAC_CTRL3_REG_s
samp_tim_rate : dac_cfg_s, DAC_CTRL3_REG_s
sample_time : adc_timer_cfg_s
SCL_MUX_SEL : BOOTLOADER_BSL_I2C_CFG_REG_s
SCL_PIN_SEL : BOOTLOADER_BSL_I2C_CFG_REG_s
SCLK_CTRL : SPI_REGS_s
sclk_removal : SPI_SCLK_CTRL_REG_s
SCR : SCB_Type
SDA_MUX_SEL : BOOTLOADER_BSL_I2C_CFG_REG_s
SDA_PIN_SEL : BOOTLOADER_BSL_I2C_CFG_REG_s
sec_bin : RTC_SEC_CTL_REG_s
SEC_CTL : RTC_REGS_s
sec_lsb_bcd : RTC_SEC_CTL_REG_s
sec_msb_bcd : RTC_SEC_CTL_REG_s
sec_rtc_rdy : RTC_SEC_CTL_REG_s
seed : CRC_CRCSEED_REG_s
sel : IOMUX_PA_REG_s
send_idle : UART_CFG_REG_s
seq_ov_dma_en : ADC_DMA_EVENT_EN_0_REG_s
seq_ov_flow : ADC_INTR_EVENT_REG_s
seq_ov_flow_en : ADC_INTR_EN_0_REG_s
seq_ov_flow_event_en : ADC_EVENT_EN_0_REG_s
seq_ov_flow_nmi_en : ADC_INTR_NMI_EN_0_REG_s
seq_ov_flow_sw_set : ADC_INTR_SW_REG_s
setup_cnt : I2C_CLK_CTRL_REG_s, i2c_counter_cfg_t
SH_CTRL : VREF_REGS_s
sh_en : VREF_CTRL_REG_s
SHCSR : SCB_Type
SHP : SCB_Type
SLAVE_ACK_CFG : I2C_REGS_s
SLAVE_ADDR : I2C_REGS_s
SLAVE_BYTE_ACK : I2C_REGS_s
SLAVE_CLKSTRETCH_CNT : I2C_REGS_s
SLAVE_CTRL : I2C_REGS_s
SLAVE_STS : I2C_REGS_s
sleep_policy_rst : WATCHDOG_WWDT_CTL0_REG_s
slew_rate : IOMUX_PA_REG_s
slv_ackval : I2C_SLAVE_BYTE_ACK_REG_s
slv_addr1 : I2C_SLAVE_ADDR_REG_s, i2c_slv_cfg_t
slv_addr2 : I2C_SLAVE_ADDR_REG_s, i2c_slv_cfg_t
slv_addr2_en : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
slv_addr2_mask : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
slv_addr2_sel : I2C_SLAVE_STS_REG_s, i2c_slv_sts_t
slv_addr_auto_ack_en : I2C_SLAVE_ACK_CFG_REG_s, i2c_slv_cfg_t
slv_addr_match : I2C_SLAVE_STS_REG_s, i2c_slv_sts_t
slv_addr_mode : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
slv_alres_addr_en : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
slv_auto_ack_en : I2C_SLAVE_ACK_CFG_REG_s, i2c_slv_cfg_t
slv_busbsy : I2C_SLAVE_STS_REG_s, i2c_slv_sts_t
slv_clkstretch_en : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
slv_crc_out_byte : I2C_CRC_OUT_BYTE_REG_s
slv_def_dev_addr_en : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
slv_def_host_addr_en : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
slv_enable : I2C_SLAVE_CTRL_REG_s
slv_gencall_en : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
slv_gencall_intr : I2C_INTR_EVENT_REG_s
slv_gencall_intr_en : I2C_INTR_EN_0_REG_s
slv_gencall_intr_nmi_en : I2C_INTR_NMI_EN_0_REG_s
slv_gencall_intr_sw_set : I2C_INTR_SW_SET_0_REG_s
slv_low_pwr_wakeup_en : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
slv_max_clkstretch_cnt : i2c_counter_cfg_t, I2C_SLAVE_CLKSTRETCH_CNT_REG_s
slv_quick_cmd_state : I2C_FSM_STATUS_REG_s
slv_rx_req : I2C_SLAVE_STS_REG_s, i2c_slv_sts_t
slv_rxmode : I2C_SLAVE_STS_REG_s, i2c_slv_sts_t
slv_stale_txfifo : I2C_SLAVE_STS_REG_s, i2c_slv_sts_t
slv_start : I2C_INTR_EVENT_REG_s
slv_start_en : I2C_INTR_EN_0_REG_s
slv_start_nmi_en : I2C_INTR_NMI_EN_0_REG_s
slv_start_sw_set : I2C_INTR_SW_SET_0_REG_s
slv_state : I2C_FSM_STATUS_REG_s
slv_stop : I2C_INTR_EVENT_REG_s
slv_stop_en : I2C_INTR_EN_0_REG_s
slv_stop_nmi_en : I2C_INTR_NMI_EN_0_REG_s
slv_stop_sw_set : I2C_INTR_SW_SET_0_REG_s
slv_tx_req : I2C_SLAVE_STS_REG_s, i2c_slv_sts_t
slv_txempty_intr_on_tx_req : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
slv_txmode : I2C_SLAVE_STS_REG_s, i2c_slv_sts_t
slv_txtrig_at_txmode : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
slv_txwait_stale_fifo : I2C_SLAVE_CTRL_REG_s, i2c_slv_cfg_t
SM_STATE : ADC_REGS_s
smbus_timeout : I2C_INTR_EVENT_REG_s
SMBUS_TIMEOUT_CNT : I2C_REGS_s
smbus_timeout_cnt : i2c_counter_cfg_t, I2C_SMBUS_TIMEOUT_CNT_REG_s
smbus_timeout_en : I2C_INTR_EN_0_REG_s
smbus_timeout_nmi_en : I2C_INTR_NMI_EN_0_REG_s
smbus_timeout_sw_set : I2C_INTR_SW_SET_0_REG_s
soft_cs : SPI_CS_CTRL_REG_s
soft_cs_en : SPI_CS_CTRL_REG_s
soft_stop : ADC_DBG_CTRL_REG_s, I2C_DBG_CTRL_REG_s, SPI_DBG_CTRL_REG_s, UART_DBG_CTRL_REG_s
SPARE_CTRL : ADC_REGS_s, COMP_REGS_s, DAC_REGS_s, I2C_REGS_s, MCU_CTRL_REGS_s, OPAMP_REGS_s, SPI_REGS_s, VREF_REGS_s
spare_in : MCU_CTRL_ANA_SPARE_STS_REG_s
spare_out_0 : MCU_CTRL_ANA_SPARE_OUT0_REG_s
spare_out_1 : MCU_CTRL_ANA_SPARE_OUT1_REG_s
SPARE_STS : ADC_REGS_s, COMP_REGS_s, DAC_REGS_s, I2C_REGS_s, MCU_CTRL_REGS_s, OPAMP_REGS_s, SPI_REGS_s, VREF_REGS_s
speed : COMP_CTRL0_REG_s
spi_busy_sts : SPI_STS_REG_s
SPI_CLK_CTRL_REG_s : SPI_CLK_CTRL_u
SPI_CLK_DIV_REG_s : SPI_CLK_DIV_u
SPI_CLKSEL_REG_s : SPI_CLKSEL_u
SPI_CMD_DATA_CTRL_REG_s : SPI_CMD_DATA_CTRL_u
SPI_CS_CTRL_REG_s : SPI_CS_CTRL_u
SPI_CS_SETUP_HOLD_CNT_REG_s : SPI_CS_SETUP_HOLD_CNT_u
SPI_DATAFRAME_CTRL_REG_s : SPI_DATAFRAME_CTRL_u
SPI_DBG_CTRL_REG_s : SPI_DBG_CTRL_u
SPI_DESC_REG_s : SPI_DESC_u
SPI_DSPI_CTRL_REG_s : SPI_DSPI_CTRL_u
spi_en : SPI_MODE_CTRL_REG_s
SPI_INT_FIFO_LVL_SEL_REG_s : SPI_INT_FIFO_LVL_SEL_u
SPI_INTR_EN_REG_s : SPI_INTR_EN_u
SPI_INTR_EVENT_REG_s : SPI_INTR_EVENT_u
SPI_INTR_NMI_REG_s : SPI_INTR_NMI_u
SPI_INTR_RX_DMA_EN_REG_s : SPI_INTR_RX_DMA_EN_u
SPI_INTR_STS_REG_s : SPI_INTR_STS_u
SPI_INTR_SW_SET_REG_s : SPI_INTR_SW_SET_u
SPI_INTR_TX_DMA_EN_REG_s : SPI_INTR_TX_DMA_EN_u
SPI_LOOPBACK_CTRL_REG_s : SPI_LOOPBACK_CTRL_u
SPI_MODE_CTRL_REG_s : SPI_MODE_CTRL_u
SPI_MOT_MOD_CNTRL_REG_s : SPI_MOT_MOD_CNTRL_u
SPI_PARITY_CTRL_REG_s : SPI_PARITY_CTRL_u
SPI_PWR_EN_REG_s : SPI_PWR_EN_u
SPI_QSPI_CTRL_REG_s : SPI_QSPI_CTRL_u
SPI_RST_CTRL_REG_s : SPI_RST_CTRL_u
SPI_RST_STS_REG_s : SPI_RST_STS_u
SPI_RX_CTRL_REG_s : SPI_RX_CTRL_u
SPI_RX_FIFO_REG_s : SPI_RX_FIFO_u
SPI_SCLK_CTRL_REG_s : SPI_SCLK_CTRL_u
SPI_SPARE_CTRL_REG_s : SPI_SPARE_CTRL_u
SPI_SPARE_STS_REG_s : SPI_SPARE_STS_u
SPI_STS_REG_s : SPI_STS_u
SPI_TX_CTRL_REG_s : SPI_TX_CTRL_u
SPI_TX_FIFO_REG_s : SPI_TX_FIFO_u
SPSEL : CONTROL_Type.b
src_addr : dma_channel_cfg_t
src_inc : dma_mem_ctrl_cfg_t, DMA_STRIDE_MODE_CFG_0_REG_s
src_incr : dma_channel_cfg_t
src_prot_ctrl : dma_channel_cfg_t, dma_mem_ctrl_cfg_t
src_size : dma_channel_cfg_t, dma_mem_ctrl_cfg_t
src_stride_val : DMA_STRIDE_MODE_CFG_0_REG_s
srl : FLASH_CTRL_REG_s
start_addr : ADC_CONV_CFG_REG_s, adc_multi_ch_conv_cfg_s, adc_single_ch_conv_cfg_s
start_time : adc_timer_cfg_s
state : PL230_DMA_STATUS_REG_s
STATUS : ADC_REGS_s, FLASH_REGS_s, VULTAN_FLASH_REGS_s
stck_par : UART_CFG_REG_s
stick_parity : uart_cfg_s
stop_bit : UART_CFG_REG_s
stop_in_sleep_mode : WATCHDOG_WWDT_CTL0_REG_s
stop_on_halt : ADC_DBG_CTRL_REG_s, SPI_DBG_CTRL_REG_s
stride_dst_incr : dma_channel_cfg_t
stride_en : dma_channel_cfg_t
STRIDE_MODE : DMA_REGS_s
STRIDE_MODE_CFG_0 : DMA_REGS_s
STRIDE_MODE_CFG_1 : DMA_REGS_s
STRIDE_MODE_CFG_2 : DMA_REGS_s
stride_mode_chnl_no : DMA_STRIDE_MODE_CFG_0_REG_s
stride_mode_dst_base_addr : DMA_STRIDE_MODE_CFG_2_REG_s
stride_mode_en : DMA_STRIDE_MODE_REG_s
stride_mode_src_base_addr : DMA_STRIDE_MODE_CFG_1_REG_s
stride_src_incr : dma_channel_cfg_t
STS : COMP_REGS_s, FLASH_REGS_s, OTP_REGS_s, SPI_REGS_s, UART_REGS_s, VREF_REGS_s
sts0 : COMP_SPARE_STS_REG_s, DAC_SPARE_STS_REG_s, I2C_SPARE_STS_REG_s, MCU_CTRL_SPARE_STS_REG_s, OPAMP_SPARE_STS_REG_s, SPI_SPARE_STS_REG_s
sts1 : COMP_SPARE_STS_REG_s, DAC_SPARE_STS_REG_s, I2C_SPARE_STS_REG_s, MCU_CTRL_SPARE_STS_REG_s, OPAMP_SPARE_STS_REG_s, SPI_SPARE_STS_REG_s
sub : event_fabric_chnl_cfg
SUB_CFG : GPIO_REGS_s
sub_en : GPIO_SUB_CFG_REG_s
SUBS_PORT : ADC_REGS_s
subs_port : ADC_SUBS_PORT_REG_s
suppress_coc_event_gen_0 : TIMER_CC0_CMN_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CMN_CTRL_REG_s
suppress_coc_event_gen_1 : TIMER_CC1_CMN_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CMN_CTRL_REG_s
suppress_coc_event_gen_2 : TIMER_CC2_CMN_CTRL_REG_s
suppress_coc_event_gen_3 : TIMER_CC3_CMN_CTRL_REG_s
suppress_coc_event_gen_4 : TIMER_CC4_CMN_CTRL_REG_s
suppress_coc_event_gen_5 : TIMER_CC5_CMN_CTRL_REG_s
suppress_ctr_event_gen : TIMER_CTR_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CTR_CTL_REG_s
sw_rst_lvl0 : MCU_CTRL_MCU_SW_RST_REG_s
sw_rst_lvl1 : MCU_CTRL_MCU_SW_RST_REG_s
sw_rst_lvl2 : MCU_CTRL_MCU_SW_RST_REG_s
sw_rst_lvl3 : MCU_CTRL_MCU_SW_RST_REG_s
sw_rst_lvl4 : MCU_CTRL_MCU_SW_RST_REG_s
SW_TRIGGER : ADC_REGS_s
sw_trigger : adc_sw_trig_cfg_s, ADC_SW_TRIGGER_REG_s
sw_trigger_en : adc_sw_trig_cfg_s, ADC_SW_TRIGGER_REG_s
SWD_EN : BOOTLOADER_BCR_CFG0_REG_s