Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

r_power : dma_channel_cfg_t, dma_mem_ctrl_cfg_t
RCTR_LOAD_VAL : TIMER_REGS_s
rctr_load_val : TIMER_RCTR_LOAD_VAL_REG_s
RCTR_VAL : TIMER_REGS_s
rctr_val : TIMER_RCTR_VAL_REG_s
rctr_zero : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
rctr_zero_en : TIMER_INTR_EN_1_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_1_REG_s
rctr_zero_event_en_0 : TIMER_EVENT_EN_0_1_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_1_REG_s
rctr_zero_event_en_1 : TIMER_EVENT_EN_1_1_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_1_REG_s
rctr_zero_nmi_en : TIMER_INTR_NMI_EN_1_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_1_REG_s
rctr_zero_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
rcv_negedge : UART_INTR_EVENT_REG_s
rcv_negedge_en : UART_INTR_EN0_REG_s
rcv_negedge_nmi_en : UART_INTR_NMI_EN0_REG_s
rcv_negedge_sw_set : UART_INTR_SW_SET_REG_s
rcv_posedge : UART_INTR_EVENT_REG_s
rcv_posedge_en : UART_INTR_EN0_REG_s
rcv_posedge_nmi_en : UART_INTR_NMI_EN0_REG_s
rcv_posedge_sw_set : UART_INTR_SW_SET_REG_s
rcv_timeout : UART_INTR_EVENT_REG_s
rcv_timeout_en : UART_INTR_EN0_REG_s
rcv_timeout_nmi_en : UART_INTR_NMI_EN0_REG_s
rcv_timeout_sw_set : UART_INTR_SW_SET_REG_s
rd_pstate : OTP_STS_REG_s
rdecc : FLASH_CTRL_REG_s
rdp : dma_mem_channel_cfg_t
read_overflow_irq : VULTAN_FLASH_IRQ_MASKED_STATUS_REG_s
read_overflow_irq_en_clr : VULTAN_FLASH_IRQ_ENABLE_CLR_REG_s
read_overflow_irq_en_set : VULTAN_FLASH_IRQ_ENABLE_SET_REG_s
read_overflow_irq_sts_clr : VULTAN_FLASH_IRQ_STATUS_CLR_REG_s
read_overflow_irq_sts_set : VULTAN_FLASH_IRQ_STATUS_SET_REG_s
receive_timeout : SPI_RX_CTRL_REG_s
REF_CTRL0 : COMP_REGS_s
REF_CTRL1 : COMP_REGS_s
ref_mode : COMP_REF_CTRL0_REG_s
ref_sel : COMP_REF_CTRL0_REG_s
ref_src : COMP_REF_CTRL0_REG_s
rem_transaction_chnl0 : DMA_EARLY_IRQ_0_REG_s
rem_transaction_chnl1 : DMA_EARLY_IRQ_1_REG_s
rem_transaction_chnl10 : DMA_EARLY_IRQ_10_REG_s
rem_transaction_chnl11 : DMA_EARLY_IRQ_11_REG_s
rem_transaction_chnl12 : DMA_EARLY_IRQ_12_REG_s
rem_transaction_chnl13 : DMA_EARLY_IRQ_13_REG_s
rem_transaction_chnl14 : DMA_EARLY_IRQ_14_REG_s
rem_transaction_chnl15 : DMA_EARLY_IRQ_15_REG_s
rem_transaction_chnl2 : DMA_EARLY_IRQ_2_REG_s
rem_transaction_chnl3 : DMA_EARLY_IRQ_3_REG_s
rem_transaction_chnl4 : DMA_EARLY_IRQ_4_REG_s
rem_transaction_chnl5 : DMA_EARLY_IRQ_5_REG_s
rem_transaction_chnl6 : DMA_EARLY_IRQ_6_REG_s
rem_transaction_chnl7 : DMA_EARLY_IRQ_7_REG_s
rem_transaction_chnl8 : DMA_EARLY_IRQ_8_REG_s
rem_transaction_chnl9 : DMA_EARLY_IRQ_9_REG_s
REMAP : SYSCTRL_REGS_s
repeat : adc_multi_ch_conv_cfg_s, adc_single_ch_conv_cfg_s, timer_ctr_cfg_t
repeat_mode : TIMER_CTR_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CTR_CTL_REG_s
repeat_tx_data : SPI_TX_CTRL_REG_s
REPEATED_TRANSFER_ALTERNATE_SEL : DMA_REGS_s
REPEATED_TRANSFER_CHNL_0 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_1 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_10 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_11 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_12 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_13 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_14 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_15 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_2 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_3 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_4 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_5 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_6 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_7 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_8 : DMA_REGS_s
REPEATED_TRANSFER_CHNL_9 : DMA_REGS_s
REPEATED_TRANSFER_EN : DMA_REGS_s
repeated_transfer_en : dma_channel_cfg_t
res : dac_cfg_s, DAC_CTRL0_REG_s
Reserved : BOOTLOADER_REGS_s, PL230_REGS_s
RESERVED0 : NVIC_Type, SCB_Type
RESERVED1 : SCB_Type
RESERVED2 : NVIC_Type
RESERVED3 : NVIC_Type
RESERVED4 : NVIC_Type
RESETOP : SYSCTRL_REGS_s
restart : WATCHDOG_WWDT_RESTART_REG_s
restart_in_closed_window : WATCHDOG_INTR_EVENT_REG_s
restart_in_closed_window_en : WATCHDOG_INTR_EN_REG_s
restart_reg_incorrect_data : WATCHDOG_INTR_EVENT_REG_s
restart_reg_incorrect_data_en : WATCHDOG_INTR_EN_REG_s
restart_reg_incorrect_data_nmi_en : WATCHDOG_INTR_NMI_EN_REG_s
restart_reg_incorrect_data_sw_set : WATCHDOG_INTR_SW_SET_REG_s
restart_within_closed_window_nmi_en : WATCHDOG_INTR_NMI_EN_REG_s
restart_within_closed_window_sw_set : WATCHDOG_INTR_SW_SET_REG_s
RESULT : ADC_REGS_s
result : ADC_RESULT_REG_s, CRC_CRCRESULT_REG_s
result0_dma_en : ADC_DMA_EVENT_EN_0_REG_s
result0_event_en : ADC_EVENT_EN_0_REG_s
result0_flag : ADC_INTR_EVENT_REG_s
result0_flag_en : ADC_INTR_EN_0_REG_s
result0_flag_nmi_en : ADC_INTR_NMI_EN_0_REG_s
result0_flag_sw_set : ADC_INTR_SW_REG_s
result10_dma_en : ADC_DMA_EVENT_EN_1_REG_s
result10_event_en : ADC_EVENT_EN_1_REG_s
result10_flag : ADC_INTR_EVENT_REG_s
result10_flag_en : ADC_INTR_EN_1_REG_s
result10_flag_nmi_en : ADC_INTR_NMI_EN_1_REG_s
result10_flag_sw_set : ADC_INTR_SW_REG_s
result11_dma_en : ADC_DMA_EVENT_EN_1_REG_s
result11_event_en : ADC_EVENT_EN_1_REG_s
result11_flag : ADC_INTR_EVENT_REG_s
result11_flag_en : ADC_INTR_EN_1_REG_s
result11_flag_nmi_en : ADC_INTR_NMI_EN_1_REG_s
result11_flag_sw_set : ADC_INTR_SW_REG_s
result12_dma_en : ADC_DMA_EVENT_EN_1_REG_s
result12_event_en : ADC_EVENT_EN_1_REG_s
result12_flag : ADC_INTR_EVENT_REG_s
result12_flag_en : ADC_INTR_EN_1_REG_s
result12_flag_nmi_en : ADC_INTR_NMI_EN_1_REG_s
result12_flag_sw_set : ADC_INTR_SW_REG_s
result13_dma_en : ADC_DMA_EVENT_EN_1_REG_s
result13_event_en : ADC_EVENT_EN_1_REG_s
result13_flag : ADC_INTR_EVENT_REG_s
result13_flag_en : ADC_INTR_EN_1_REG_s
result13_flag_nmi_en : ADC_INTR_NMI_EN_1_REG_s
result13_flag_sw_set : ADC_INTR_SW_REG_s
result14_dma_en : ADC_DMA_EVENT_EN_1_REG_s
result14_event_en : ADC_EVENT_EN_1_REG_s
result14_flag : ADC_INTR_EVENT_REG_s
result14_flag_en : ADC_INTR_EN_1_REG_s
result14_flag_nmi_en : ADC_INTR_NMI_EN_1_REG_s
result14_flag_sw_set : ADC_INTR_SW_REG_s
result15_dma_en : ADC_DMA_EVENT_EN_1_REG_s
result15_event_en : ADC_EVENT_EN_1_REG_s
result15_flag : ADC_INTR_EVENT_REG_s
result15_flag_en : ADC_INTR_EN_1_REG_s
result15_flag_nmi_en : ADC_INTR_NMI_EN_1_REG_s
result15_flag_sw_set : ADC_INTR_SW_REG_s
result1_dma_en : ADC_DMA_EVENT_EN_0_REG_s
result1_event_en : ADC_EVENT_EN_0_REG_s
result1_flag : ADC_INTR_EVENT_REG_s
result1_flag_en : ADC_INTR_EN_0_REG_s
result1_flag_nmi_en : ADC_INTR_NMI_EN_0_REG_s
result1_flag_sw_set : ADC_INTR_SW_REG_s
result2_dma_en : ADC_DMA_EVENT_EN_0_REG_s
result2_event_en : ADC_EVENT_EN_0_REG_s
result2_flag : ADC_INTR_EVENT_REG_s
result2_flag_en : ADC_INTR_EN_0_REG_s
result2_flag_nmi_en : ADC_INTR_NMI_EN_0_REG_s
result2_flag_sw_set : ADC_INTR_SW_REG_s
result3_dma_en : ADC_DMA_EVENT_EN_0_REG_s
result3_event_en : ADC_EVENT_EN_0_REG_s
result3_flag : ADC_INTR_EVENT_REG_s
result3_flag_en : ADC_INTR_EN_0_REG_s
result3_flag_nmi_en : ADC_INTR_NMI_EN_0_REG_s
result3_flag_sw_set : ADC_INTR_SW_REG_s
result4_dma_en : ADC_DMA_EVENT_EN_0_REG_s
result4_event_en : ADC_EVENT_EN_0_REG_s
result4_flag : ADC_INTR_EVENT_REG_s
result4_flag_en : ADC_INTR_EN_0_REG_s
result4_flag_nmi_en : ADC_INTR_NMI_EN_0_REG_s
result4_flag_sw_set : ADC_INTR_SW_REG_s
result5_dma_en : ADC_DMA_EVENT_EN_0_REG_s
result5_event_en : ADC_EVENT_EN_0_REG_s
result5_flag : ADC_INTR_EVENT_REG_s
result5_flag_en : ADC_INTR_EN_0_REG_s
result5_flag_nmi_en : ADC_INTR_NMI_EN_0_REG_s
result5_flag_sw_set : ADC_INTR_SW_REG_s
result6_dma_en : ADC_DMA_EVENT_EN_0_REG_s
result6_event_en : ADC_EVENT_EN_0_REG_s
result6_flag : ADC_INTR_EVENT_REG_s
result6_flag_en : ADC_INTR_EN_0_REG_s
result6_flag_nmi_en : ADC_INTR_NMI_EN_0_REG_s
result6_flag_sw_set : ADC_INTR_SW_REG_s
result7_dma_en : ADC_DMA_EVENT_EN_0_REG_s
result7_event_en : ADC_EVENT_EN_0_REG_s
result7_flag : ADC_INTR_EVENT_REG_s
result7_flag_en : ADC_INTR_EN_0_REG_s
result7_flag_nmi_en : ADC_INTR_NMI_EN_0_REG_s
result7_flag_sw_set : ADC_INTR_SW_REG_s
result8_dma_en : ADC_DMA_EVENT_EN_1_REG_s
result8_event_en : ADC_EVENT_EN_1_REG_s
result8_flag : ADC_INTR_EVENT_REG_s
result8_flag_en : ADC_INTR_EN_1_REG_s
result8_flag_nmi_en : ADC_INTR_NMI_EN_1_REG_s
result8_flag_sw_set : ADC_INTR_SW_REG_s
result9_dma_en : ADC_DMA_EVENT_EN_1_REG_s
result9_event_en : ADC_EVENT_EN_1_REG_s
result9_flag : ADC_INTR_EVENT_REG_s
result9_flag_en : ADC_INTR_EN_1_REG_s
result9_flag_nmi_en : ADC_INTR_NMI_EN_1_REG_s
result9_flag_sw_set : ADC_INTR_SW_REG_s
RESULT_CFG : ADC_REGS_s
rptd_trnsfr_alternate_sel : DMA_REPEATED_TRANSFER_ALTERNATE_SEL_REG_s
rptd_trnsfr_en : DMA_REPEATED_TRANSFER_EN_REG_s
rptd_trnsfr_total_transaction_chnl0 : DMA_REPEATED_TRANSFER_CHNL_0_REG_s
rptd_trnsfr_total_transaction_chnl1 : DMA_REPEATED_TRANSFER_CHNL_1_REG_s
rptd_trnsfr_total_transaction_chnl10 : DMA_REPEATED_TRANSFER_CHNL_10_REG_s
rptd_trnsfr_total_transaction_chnl11 : DMA_REPEATED_TRANSFER_CHNL_11_REG_s
rptd_trnsfr_total_transaction_chnl12 : DMA_REPEATED_TRANSFER_CHNL_12_REG_s
rptd_trnsfr_total_transaction_chnl13 : DMA_REPEATED_TRANSFER_CHNL_13_REG_s
rptd_trnsfr_total_transaction_chnl14 : DMA_REPEATED_TRANSFER_CHNL_14_REG_s
rptd_trnsfr_total_transaction_chnl15 : DMA_REPEATED_TRANSFER_CHNL_15_REG_s
rptd_trnsfr_total_transaction_chnl2 : DMA_REPEATED_TRANSFER_CHNL_2_REG_s
rptd_trnsfr_total_transaction_chnl3 : DMA_REPEATED_TRANSFER_CHNL_3_REG_s
rptd_trnsfr_total_transaction_chnl4 : DMA_REPEATED_TRANSFER_CHNL_4_REG_s
rptd_trnsfr_total_transaction_chnl5 : DMA_REPEATED_TRANSFER_CHNL_5_REG_s
rptd_trnsfr_total_transaction_chnl6 : DMA_REPEATED_TRANSFER_CHNL_6_REG_s
rptd_trnsfr_total_transaction_chnl7 : DMA_REPEATED_TRANSFER_CHNL_7_REG_s
rptd_trnsfr_total_transaction_chnl8 : DMA_REPEATED_TRANSFER_CHNL_8_REG_s
rptd_trnsfr_total_transaction_chnl9 : DMA_REPEATED_TRANSFER_CHNL_9_REG_s
rri_en : OPAMP_CTRL0_REG_s
RSERVED1 : NVIC_Type
rsp : dma_mem_channel_cfg_t
rst : ADC_RST_CTRL_REG_s, COMP_RST_CTRL_REG_s, CRC_RST_CTRL_REG_s, DAC_RST_CTRL_REG_s, DMA_RST_CTRL_REG_s, EVENT_FABRIC_RST_CTRL_REG_s, GPIO_RST_CTRL_REG_s, I2C_RST_CTRL_REG_s, MCU_CTRL_RST_CTRL_REG_s, OPAMP_RST_CTRL_REG_s, RTC_RST_CTRL_REG_s, SPI_RST_CTRL_REG_s, TIMER_RST_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_RST_CTRL_REG_s, UART_RST_CTRL_REG_s, VREF_RST_CTRL_REG_s, WATCHDOG_RST_CTRL_REG_s
RST_CTRL : ADC_REGS_s, COMP_REGS_s, CRC_REGS_s, DAC_REGS_s, DMA_REGS_s, EVENT_FABRIC_REGS_s, GPIO_REGS_s, I2C_REGS_s, MCU_CTRL_REGS_s, OPAMP_REGS_s, RTC_REGS_s, SPI_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_REGS_s, TIMER_TIMG_NUM_INPUT2_RST_CTRL_u, UART_REGS_s, VREF_REGS_s, WATCHDOG_REGS_s
rst_key : ADC_RST_CTRL_REG_s, COMP_RST_CTRL_REG_s, CRC_RST_CTRL_REG_s, DAC_RST_CTRL_REG_s, DMA_RST_CTRL_REG_s, EVENT_FABRIC_RST_CTRL_REG_s, GPIO_RST_CTRL_REG_s, I2C_RST_CTRL_REG_s, MCU_CTRL_RST_CTRL_REG_s, OPAMP_RST_CTRL_REG_s, RTC_RST_CTRL_REG_s, SPI_RST_CTRL_REG_s, TIMER_RST_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_RST_CTRL_REG_s, UART_RST_CTRL_REG_s, VREF_RST_CTRL_REG_s, WATCHDOG_RST_CTRL_REG_s
RST_STS : ADC_REGS_s, COMP_REGS_s, CRC_REGS_s, DAC_REGS_s, DMA_REGS_s, EVENT_FABRIC_REGS_s, GPIO_REGS_s, I2C_REGS_s, MCU_CTRL_REGS_s, OPAMP_REGS_s, RTC_REGS_s, SPI_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_REGS_s, TIMER_TIMG_NUM_INPUT2_RST_STS_u, UART_REGS_s, VREF_REGS_s, WATCHDOG_REGS_s
rst_sts : ADC_RST_STS_REG_s, COMP_RST_STS_REG_s, CRC_RST_STS_REG_s, DAC_RST_STS_REG_s, DMA_RST_STS_REG_s, EVENT_FABRIC_RST_STS_REG_s, GPIO_RST_STS_REG_s, I2C_RST_STS_REG_s, MCU_CTRL_RST_STS_REG_s, OPAMP_RST_STS_REG_s, RTC_RST_STS_REG_s, SPI_RST_STS_REG_s, TIMER_RST_STS_REG_s, TIMER_TIMG_NUM_INPUT2_RST_STS_REG_s, UART_RST_STS_REG_s, VREF_RST_STS_REG_s, WATCHDOG_RST_STS_REG_s
rst_sts_clr : ADC_RST_CTRL_REG_s, COMP_RST_CTRL_REG_s, CRC_RST_CTRL_REG_s, DAC_RST_CTRL_REG_s, DMA_RST_CTRL_REG_s, EVENT_FABRIC_RST_CTRL_REG_s, GPIO_RST_CTRL_REG_s, I2C_RST_CTRL_REG_s, MCU_CTRL_RST_CTRL_REG_s, OPAMP_RST_CTRL_REG_s, RTC_RST_CTRL_REG_s, SPI_RST_CTRL_REG_s, TIMER_RST_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_RST_CTRL_REG_s, UART_RST_CTRL_REG_s, VREF_RST_CTRL_REG_s, WATCHDOG_RST_CTRL_REG_s
RSTINFO : SYSCTRL_REGS_s
rsvd : dma_mem_channel_cfg_t
rsvd_0 : ADC_PWR_EN_REG_s, ADC_RST_CTRL_REG_s, COMP_CTRL0_REG_s, COMP_INPUT_CTRL0_REG_s, COMP_INPUT_CTRL1_REG_s, COMP_OUT_CTRL0_REG_s, COMP_OUT_CTRL1_REG_s, COMP_PWR_EN_REG_s, COMP_REF_CTRL0_REG_s, COMP_REF_CTRL1_REG_s, COMP_RST_CTRL_REG_s, CRC_PWR_EN_REG_s, CRC_RST_CTRL_REG_s, DAC_CAL_STS_REG_s, DAC_CTRL0_REG_s, DAC_CTRL1_REG_s, DAC_CTRL2_REG_s, DAC_CTRL3_REG_s, DAC_PWR_EN_REG_s, DAC_RST_CTRL_REG_s, DMA_PWR_EN_REG_s, DMA_RST_CTRL_REG_s, EVENT_FABRIC_PWR_EN_REG_s, EVENT_FABRIC_RST_CTRL_REG_s, GPIO_DIN_11_8_REG_s, GPIO_DIN_15_12_REG_s, GPIO_DIN_19_16_REG_s, GPIO_DIN_23_20_REG_s, GPIO_DIN_27_24_REG_s, GPIO_DIN_31_28_REG_s, GPIO_DIN_3_0_REG_s, GPIO_DIN_7_4_REG_s, GPIO_DOUT_11_8_REG_s, GPIO_DOUT_15_12_REG_s, GPIO_DOUT_19_16_REG_s, GPIO_DOUT_23_20_REG_s, GPIO_DOUT_27_24_REG_s, GPIO_DOUT_31_28_REG_s, GPIO_DOUT_3_0_REG_s, GPIO_DOUT_7_4_REG_s, GPIO_PWR_EN_REG_s, GPIO_RST_CTRL_REG_s, GPIO_SUB_CFG_REG_s, I2C_FIFO_CTRL_REG_s, I2C_MASTER_CTRL_REG_s, I2C_PWR_EN_REG_s, I2C_RST_CTRL_REG_s, I2C_SLAVE_ADDR_REG_s, IOMUX_PA_REG_s, MCU_CTRL_AHB_HCLK_CTRL_REG_s, MCU_CTRL_ANA_CLK_EN_REG_s, MCU_CTRL_AON_CTRL_REG_s, MCU_CTRL_BOOT_CFG_REG_s, MCU_CTRL_BOR_MODE_SEL_REG_s, MCU_CTRL_CLK_PWR_EN_REG_s, MCU_CTRL_GPAMPCTL_REG_s, MCU_CTRL_HF_CLK_CTRL_REG_s, MCU_CTRL_LF_CLK_CTRL_REG_s, MCU_CTRL_PLL_CTRL1_REG_s, MCU_CTRL_PLL_EN_REG_s, MCU_CTRL_PWR_SM_OVRD_CTL_REG_s, MCU_CTRL_RST_CTRL_REG_s, OPAMP_CTRL0_REG_s, OPAMP_GAIN_CTRL0_REG_s, OPAMP_PWR_EN_REG_s, OPAMP_RST_CTRL_REG_s, PL230_DMA_CFG_REG_s, PL230_DMA_STATUS_REG_s, RTC_BUS_CLK_FORCE_REG_s, RTC_PWR_EN_REG_s, RTC_RST_CTRL_REG_s, SPI_CMD_DATA_CTRL_REG_s, SPI_CS_CTRL_REG_s, SPI_DATAFRAME_CTRL_REG_s, SPI_DSPI_CTRL_REG_s, SPI_INT_FIFO_LVL_SEL_REG_s, SPI_MODE_CTRL_REG_s, SPI_MOT_MOD_CNTRL_REG_s, SPI_PARITY_CTRL_REG_s, SPI_PWR_EN_REG_s, SPI_QSPI_CTRL_REG_s, SPI_RST_CTRL_REG_s, TIMER_PWR_EN_REG_s, TIMER_RST_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_PWR_EN_REG_s, TIMER_TIMG_NUM_INPUT2_RST_CTRL_REG_s, UART_CLKCFG_REG_s, UART_PWR_EN_REG_s, UART_RST_CTRL_REG_s, VREF_CLK_CTRL_REG_s, VREF_CTRL_REG_s, VREF_PWR_EN_REG_s, VREF_RST_CTRL_REG_s, VULTAN_FLASH_CTRL_REG_s, WATCHDOG_PWR_EN_REG_s, WATCHDOG_RST_CTRL_REG_s, WATCHDOG_WWDT_CTL0_REG_s, WATCHDOG_WWDT_CTL1_REG_s, WATCHDOG_WWDT_EN_REG_s
rsvd_1 : COMP_CTRL0_REG_s, COMP_INPUT_CTRL0_REG_s, COMP_OUT_CTRL0_REG_s, COMP_OUT_CTRL1_REG_s, COMP_REF_CTRL0_REG_s, DAC_CTRL0_REG_s, DAC_CTRL1_REG_s, DAC_CTRL2_REG_s, GPIO_DIN_11_8_REG_s, GPIO_DIN_15_12_REG_s, GPIO_DIN_19_16_REG_s, GPIO_DIN_23_20_REG_s, GPIO_DIN_27_24_REG_s, GPIO_DIN_31_28_REG_s, GPIO_DIN_3_0_REG_s, GPIO_DIN_7_4_REG_s, GPIO_DOUT_11_8_REG_s, GPIO_DOUT_15_12_REG_s, GPIO_DOUT_19_16_REG_s, GPIO_DOUT_23_20_REG_s, GPIO_DOUT_27_24_REG_s, GPIO_DOUT_31_28_REG_s, GPIO_DOUT_3_0_REG_s, GPIO_DOUT_7_4_REG_s, GPIO_SUB_CFG_REG_s, I2C_FIFO_CTRL_REG_s, I2C_MASTER_CTRL_REG_s, MCU_CTRL_AHB_HCLK_CTRL_REG_s, MCU_CTRL_ANA_CLK_EN_REG_s, MCU_CTRL_AON_CTRL_REG_s, MCU_CTRL_CLK_PWR_EN_REG_s, MCU_CTRL_GPAMPCTL_REG_s, MCU_CTRL_HF_CLK_CTRL_REG_s, MCU_CTRL_LF_CLK_CTRL_REG_s, MCU_CTRL_PLL_CTRL1_REG_s, MCU_CTRL_PLL_EN_REG_s, MCU_CTRL_PWR_SM_OVRD_CTL_REG_s, OPAMP_CTRL0_REG_s, OPAMP_GAIN_CTRL0_REG_s, PL230_DMA_STATUS_REG_s, SPI_CS_CTRL_REG_s, SPI_DATAFRAME_CTRL_REG_s, SPI_MODE_CTRL_REG_s, VREF_CTRL_REG_s
rsvd_2 : COMP_CTRL0_REG_s, COMP_INPUT_CTRL0_REG_s, COMP_OUT_CTRL0_REG_s, COMP_OUT_CTRL1_REG_s, DAC_CTRL1_REG_s, DAC_CTRL2_REG_s, GPIO_DIN_11_8_REG_s, GPIO_DIN_15_12_REG_s, GPIO_DIN_19_16_REG_s, GPIO_DIN_23_20_REG_s, GPIO_DIN_27_24_REG_s, GPIO_DIN_31_28_REG_s, GPIO_DIN_3_0_REG_s, GPIO_DIN_7_4_REG_s, GPIO_DOUT_11_8_REG_s, GPIO_DOUT_15_12_REG_s, GPIO_DOUT_19_16_REG_s, GPIO_DOUT_23_20_REG_s, GPIO_DOUT_27_24_REG_s, GPIO_DOUT_31_28_REG_s, GPIO_DOUT_3_0_REG_s, GPIO_DOUT_7_4_REG_s, MCU_CTRL_CLK_PWR_EN_REG_s, MCU_CTRL_HF_CLK_CTRL_REG_s, MCU_CTRL_LF_CLK_CTRL_REG_s, MCU_CTRL_PLL_CTRL1_REG_s, MCU_CTRL_PLL_EN_REG_s, MCU_CTRL_PWR_SM_OVRD_CTL_REG_s, OPAMP_CTRL0_REG_s, OPAMP_GAIN_CTRL0_REG_s, PL230_DMA_STATUS_REG_s
rsvd_3 : MCU_CTRL_CLK_PWR_EN_REG_s, MCU_CTRL_HF_CLK_CTRL_REG_s, MCU_CTRL_LF_CLK_CTRL_REG_s, MCU_CTRL_PLL_EN_REG_s, MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
rsvd_4 : MCU_CTRL_PLL_EN_REG_s, MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
RTC_A0_DAY_REG_s : RTC_A0_DAY_u
RTC_A0_HOUR_REG_s : RTC_A0_HOUR_u
RTC_A0_MIN_REG_s : RTC_A0_MIN_u
RTC_A1_DAY_REG_s : RTC_A1_DAY_u
RTC_A1_HOUR_REG_s : RTC_A1_HOUR_u
RTC_A1_MIN_REG_s : RTC_A1_MIN_u
rtc_bcd : RTC_RTC_CTL_REG_s
RTC_BUS_CLK_FORCE_REG_s : RTC_BUS_CLK_FORCE_u
RTC_CAL : RTC_REGS_s
rtc_cal_sign : RTC_REF_DATA_s
rtc_clk_cal : RTC_REF_DATA_s
RTC_CLK_CTRL_REG_s : RTC_CLK_CTRL_u
RTC_CTL : RTC_REGS_s
RTC_DEBUG_CTL_REG_s : RTC_DEBUG_CTL_u
RTC_DESC_REG_s : RTC_DESC_u
RTC_DOM_CTL_REG_s : RTC_DOM_CTL_u
RTC_DOW_CTL_REG_s : RTC_DOW_CTL_u
RTC_EVENT_EN_REG_s : RTC_EVENT_EN_u
rtc_exp_dom : RTC_REF_DATA_s
rtc_exp_dow : RTC_REF_DATA_s
rtc_exp_hr : RTC_REF_DATA_s
rtc_exp_min : RTC_REF_DATA_s
rtc_exp_mon : RTC_REF_DATA_s
rtc_exp_sec : RTC_REF_DATA_s
rtc_exp_year : RTC_REF_DATA_s
RTC_HR_CTL_REG_s : RTC_HR_CTL_u
RTC_INTERVAL_INTR_SEL_REG_s : RTC_INTERVAL_INTR_SEL_u
RTC_INTR_EN_REG_s : RTC_INTR_EN_u
RTC_INTR_EVENT_REG_s : RTC_INTR_EVENT_u
RTC_INTR_NMI_EN_REG_s : RTC_INTR_NMI_EN_u
RTC_INTR_STS_REG_s : RTC_INTR_STS_u
RTC_INTR_SW_SET_REG_s : RTC_INTR_SW_SET_u
RTC_MIN_CTL_REG_s : RTC_MIN_CTL_u
RTC_MON_CTL_REG_s : RTC_MON_CTL_u
RTC_PRD_INTR_SEL0_REG_s : RTC_PRD_INTR_SEL0_u
RTC_PRD_INTR_SEL1_REG_s : RTC_PRD_INTR_SEL1_u
RTC_PWR_EN_REG_s : RTC_PWR_EN_u
rtc_rdy : RTC_INTR_EVENT_REG_s
rtc_rdy_en : RTC_INTR_EN_REG_s
rtc_rdy_event_en : RTC_EVENT_EN_REG_s
rtc_rdy_nmi_en : RTC_INTR_NMI_EN_REG_s
rtc_rdy_sw_set : RTC_INTR_SW_SET_REG_s
RTC_RST_CTRL_REG_s : RTC_RST_CTRL_u
RTC_RST_STS_REG_s : RTC_RST_STS_u
RTC_RTC_CAL_REG_s : RTC_RTC_CAL_u
RTC_RTC_CTL_REG_s : RTC_RTC_CTL_u
RTC_RTC_TEMP_CMP_REG_s : RTC_RTC_TEMP_CMP_u
RTC_SEC_CTL_REG_s : RTC_SEC_CTL_u
rtc_temp_cal : RTC_REF_DATA_s
RTC_TEMP_CMP : RTC_REGS_s
rtc_temp_sign : RTC_REF_DATA_s
rtc_time_dom : RTC_REF_DATA_s
rtc_time_dow : RTC_REF_DATA_s
rtc_time_hr : RTC_REF_DATA_s
rtc_time_min : RTC_REF_DATA_s
rtc_time_mon : RTC_REF_DATA_s
rtc_time_sec : RTC_REF_DATA_s
rtc_time_year : RTC_REF_DATA_s
RTC_YEAR_CTL_REG_s : RTC_YEAR_CTL_u
rts_en : uart_cfg_s, UART_CTRL_REG_s
rts_val : uart_cfg_s, UART_CTRL_REG_s
rtw : FLASH_TIME_CTRL_1_REG_s
run : WATCHDOG_WWDT_STS_REG_s
run_in_halt_mode : TIMER_DEBUG_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_DEBUG_CTRL_REG_s, WATCHDOG_HALT_MODE_REG_s
run_on_halt : I2C_DBG_CTRL_REG_s, UART_DBG_CTRL_REG_s
RX_CTRL : SPI_REGS_s
rx_dma_arb_lost_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_clkstretch_timeout_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_dma_done_rx_en : I2C_RX_DMA_EVENT_EN_1_REG_s
rx_dma_dma_done_tx_en : I2C_RX_DMA_EVENT_EN_1_REG_s
rx_dma_done : SPI_INTR_EVENT_REG_s
rx_dma_done_en : SPI_INTR_EN_REG_s
rx_dma_done_nmi_en : SPI_INTR_NMI_REG_s
rx_dma_done_rx_dma_en : SPI_INTR_RX_DMA_EN_REG_s
rx_dma_done_sw_set : SPI_INTR_SW_SET_REG_s
rx_dma_done_tx_dma_en : SPI_INTR_TX_DMA_EN_REG_s
RX_DMA_EVENT_EN_0 : I2C_REGS_s
RX_DMA_EVENT_EN_1 : I2C_REGS_s
rx_dma_mst_nack_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_mst_start_intr_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_mst_stop_intr_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_pec_err_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_rx_done_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_rxfifo_almost_full_intr_en : I2C_RX_DMA_EVENT_EN_1_REG_s
rx_dma_rxfifo_full_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_rxfifo_half_full_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_slv_gencall_intr_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_slv_start_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_slv_stop_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_smbus_timeout_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_tx_done_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_txfifo_almost_empty_intr_en : I2C_RX_DMA_EVENT_EN_1_REG_s
rx_dma_txfifo_empty_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_dma_txfifo_half_full_en : I2C_RX_DMA_EVENT_EN_0_REG_s
rx_done : I2C_INTR_EVENT_REG_s
rx_done_en : I2C_INTR_EN_0_REG_s
rx_done_nmi_en : I2C_INTR_NMI_EN_0_REG_s
rx_done_sw_set : I2C_INTR_SW_SET_0_REG_s
rx_en : uart_cfg_s, UART_CTRL_REG_s
RX_FIFO : SPI_REGS_s
rx_fifo : SPI_RX_FIFO_REG_s
rx_fifo_almost_empty : UART_INTR_EVENT_REG_s
rx_fifo_almost_empty_en : UART_INTR_EN0_REG_s
rx_fifo_almost_empty_nmi_en : UART_INTR_NMI_EN0_REG_s
rx_fifo_almost_empty_sts : UART_FIFOSTS_REG_s
rx_fifo_almost_empty_sw_set : UART_INTR_SW_SET_REG_s
rx_fifo_almost_full : UART_INTR_EVENT_REG_s
rx_fifo_almost_full_en : UART_INTR_EN0_REG_s
rx_fifo_almost_full_nmi_en : UART_INTR_NMI_EN0_REG_s
rx_fifo_almost_full_sts : UART_FIFOSTS_REG_s
rx_fifo_almost_full_sw_set : UART_INTR_SW_SET_REG_s
rx_fifo_empty : UART_INTR_EVENT_REG_s
rx_fifo_empty_en : UART_INTR_EN0_REG_s
rx_fifo_empty_nmi_en : UART_INTR_NMI_EN0_REG_s
rx_fifo_empty_sts : SPI_STS_REG_s, UART_FIFOSTS_REG_s
rx_fifo_empty_sw_set : UART_INTR_SW_SET_REG_s
rx_fifo_full : SPI_INTR_EVENT_REG_s, UART_INTR_EVENT_REG_s
rx_fifo_full_en : SPI_INTR_EN_REG_s, UART_INTR_EN0_REG_s
rx_fifo_full_nmi_en : SPI_INTR_NMI_REG_s, UART_INTR_NMI_EN0_REG_s
rx_fifo_full_rx_dma_en : SPI_INTR_RX_DMA_EN_REG_s
rx_fifo_full_sts : SPI_STS_REG_s, UART_FIFOSTS_REG_s
rx_fifo_full_sw_set : SPI_INTR_SW_SET_REG_s, UART_INTR_SW_SET_REG_s
rx_fifo_full_tx_dma_en : SPI_INTR_TX_DMA_EN_REG_s
rx_fifo_ls : UART_FIFOLS_REG_s
rx_fifo_lvl_int : SPI_INT_FIFO_LVL_SEL_REG_s
rx_fifo_lvl_sel : uart_fifo_cfg_s
rx_fifo_overflow : SPI_INTR_EVENT_REG_s
rx_fifo_overflow_en : SPI_INTR_EN_REG_s
rx_fifo_overflow_nmi_en : SPI_INTR_NMI_REG_s
rx_fifo_overflow_rx_dma_en : SPI_INTR_RX_DMA_EN_REG_s
rx_fifo_overflow_sw_set : SPI_INTR_SW_SET_REG_s
rx_fifo_overflow_tx_dma_en : SPI_INTR_TX_DMA_EN_REG_s
rx_fifo_trg_lvl : SPI_INTR_EVENT_REG_s
rx_fifo_trg_lvl_en : SPI_INTR_EN_REG_s
rx_fifo_trg_lvl_nmi_en : SPI_INTR_NMI_REG_s
rx_fifo_trg_lvl_rx_dma_en : SPI_INTR_RX_DMA_EN_REG_s
rx_fifo_trg_lvl_sw_set : SPI_INTR_SW_SET_REG_s
rx_fifo_trg_lvl_tx_dma_en : SPI_INTR_TX_DMA_EN_REG_s
rx_int : UART_INTR_EVENT_REG_s
rx_int_en : UART_INTR_EN1_REG_s
rx_int_nmi_en : UART_INTR_NMI_EN1_REG_s
rx_int_sw_set : UART_INTR_SW_SET_REG_s
rx_state : UART_FSM_STS_REG_s
rx_timeout : SPI_INTR_EVENT_REG_s
rx_timeout_en : SPI_INTR_EN_REG_s
rx_timeout_nmi_en : SPI_INTR_NMI_REG_s
rx_timeout_rx_dma_en : SPI_INTR_RX_DMA_EN_REG_s
rx_timeout_sw_set : SPI_INTR_SW_SET_REG_s
rx_timeout_tx_dma_en : SPI_INTR_TX_DMA_EN_REG_s
rx_timeout_val : uart_cfg_s
rx_to : UART_FIFOLS_REG_s
RXDATA : I2C_REGS_s, UART_REGS_s
rxdata : I2C_RXDATA_REG_s
rxfifo_almost_full : I2C_FIFO_STS_REG_s
rxfifo_almost_full_intr : I2C_INTR_EVENT_REG_s
rxfifo_almost_full_intr_en : I2C_INTR_EN_1_REG_s
rxfifo_almost_full_intr_nmi_en : I2C_INTR_NMI_EN_1_REG_s
rxfifo_almost_full_intr_sw_set : I2C_INTR_SW_SET_1_REG_s
rxfifo_empty : I2C_FIFO_STS_REG_s
rxfifo_en : I2C_FIFO_CTRL_REG_s, i2c_slv_cfg_t
rxfifo_flush : I2C_FIFO_CTRL_REG_s
rxfifo_flush_sts : I2C_FIFO_STS_REG_s
rxfifo_full : I2C_INTR_EVENT_REG_s
rxfifo_full_en : I2C_INTR_EN_0_REG_s
rxfifo_full_nmi_en : I2C_INTR_NMI_EN_0_REG_s
rxfifo_full_sts : I2C_FIFO_STS_REG_s
rxfifo_full_sw_set : I2C_INTR_SW_SET_0_REG_s
rxfifo_half_full : I2C_INTR_EVENT_REG_s
rxfifo_half_full_en : I2C_INTR_EN_0_REG_s
rxfifo_half_full_nmi_en : I2C_INTR_NMI_EN_0_REG_s
rxfifo_half_full_sw_set : I2C_INTR_SW_SET_0_REG_s