Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

C : APSR_Type.b, xPSR_Type.b
CAL_CTRL : DAC_REGS_s
cal_ctrl : ADC_CALIBRATION_REQ_REG_s
cal_data : DAC_CAL_STS_REG_s
cal_done : ADC_CALIBRATION_REQ_REG_s, DAC_CAL_STS_REG_s
cal_en : DAC_CAL_CTRL_REG_s
cal_req : ADC_CALIBRATION_REQ_REG_s
cal_sel : DAC_CAL_CTRL_REG_s
CAL_STS : DAC_REGS_s
CALIB : SysTick_Type
CALIBRATION_REQ : ADC_REGS_s
cap_chan_ctrl : timer_pwm_cfg_t
cap_cond : timer_capture_channel_ctrl_t
cap_cond_0 : TIMER_CC0_CAPTURE_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CAPTURE_CTRL_REG_s
cap_cond_1 : TIMER_CC1_CAPTURE_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CAPTURE_CTRL_REG_s
cap_cond_2 : TIMER_CC2_CAPTURE_CTRL_REG_s
cap_cond_3 : TIMER_CC3_CAPTURE_CTRL_REG_s
cap_val_0 : TIMER_CC0_CAPTURE_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CAPTURE_CTRL_REG_s
cap_val_1 : TIMER_CC1_CAPTURE_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CAPTURE_CTRL_REG_s
cap_val_2 : TIMER_CC2_CAPTURE_CTRL_REG_s
cap_val_3 : TIMER_CC3_CAPTURE_CTRL_REG_s
CC0_CAPTURE_CTRL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC0_CAPTURE_CTRL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC0_CC_PWM_CFG : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC0_CMN_CTRL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC0_CMN_CTRL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC0_COMPARE_CTRL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC0_COMPARE_CTRL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC0_OUTPUT_CTL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC0_OUTPUT_CTL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC0_SW_FORCE : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC0_SW_FORCE_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC1_CAPTURE_CTRL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC1_CAPTURE_CTRL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC1_CC_PWM_CFG : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC1_CMN_CTRL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC1_CMN_CTRL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC1_COMPARE_CTRL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC1_COMPARE_CTRL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC1_OUTPUT_CTL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC1_OUTPUT_CTL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC1_SW_FORCE : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CC1_SW_FORCE_u, TIMER_TIMG_NUM_INPUT2_REGS_s
CC2_CAPTURE_CTRL : TIMER_REGS_s
CC2_CC_PWM_CFG : TIMER_REGS_s
CC2_CMN_CTRL : TIMER_REGS_s
CC2_COMPARE_CTRL : TIMER_REGS_s
CC2_OUTPUT_CTL : TIMER_REGS_s
CC2_SW_FORCE : TIMER_REGS_s
cc2d_act : timer_pwm_output_channel_action_cfg_t
cc2d_sel_0 : TIMER_CC0_CMN_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CMN_CTRL_REG_s
cc2d_sel_1 : TIMER_CC1_CMN_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CMN_CTRL_REG_s
cc2d_sel_2 : TIMER_CC2_CMN_CTRL_REG_s
cc2d_sel_3 : TIMER_CC3_CMN_CTRL_REG_s
cc2u_act : timer_pwm_output_channel_action_cfg_t
cc2u_sel_0 : TIMER_CC0_CMN_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CMN_CTRL_REG_s
cc2u_sel_1 : TIMER_CC1_CMN_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CMN_CTRL_REG_s
cc2u_sel_2 : TIMER_CC2_CMN_CTRL_REG_s
cc2u_sel_3 : TIMER_CC3_CMN_CTRL_REG_s
CC3_CAPTURE_CTRL : TIMER_REGS_s
CC3_CC_PWM_CFG : TIMER_REGS_s
CC3_CMN_CTRL : TIMER_REGS_s
CC3_COMPARE_CTRL : TIMER_REGS_s
CC3_OUTPUT_CTL : TIMER_REGS_s
CC3_SW_FORCE : TIMER_REGS_s
CC4_CMN_CTRL : TIMER_REGS_s
CC4_COMPARE_CTRL : TIMER_REGS_s
CC5_CMN_CTRL : TIMER_REGS_s
CC5_COMPARE_CTRL : TIMER_REGS_s
cc_cmpl_out_sw_force_0 : TIMER_CC0_SW_FORCE_REG_s
cc_cmpl_out_sw_force_1 : TIMER_CC1_SW_FORCE_REG_s
cc_cmpl_out_sw_force_2 : TIMER_CC2_SW_FORCE_REG_s
cc_cmpl_out_sw_force_3 : TIMER_CC3_SW_FORCE_REG_s
cc_out_cc2d_0 : TIMER_CC0_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_REG_s
cc_out_cc2d_1 : TIMER_CC1_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_REG_s
cc_out_cc2d_2 : TIMER_CC2_CC_PWM_CFG_REG_s
cc_out_cc2d_3 : TIMER_CC3_CC_PWM_CFG_REG_s
cc_out_cc2u_0 : TIMER_CC0_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_REG_s
cc_out_cc2u_1 : TIMER_CC1_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_REG_s
cc_out_cc2u_2 : TIMER_CC2_CC_PWM_CFG_REG_s
cc_out_cc2u_3 : TIMER_CC3_CC_PWM_CFG_REG_s
cc_out_ccd_0 : TIMER_CC0_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_REG_s
cc_out_ccd_1 : TIMER_CC1_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_REG_s
cc_out_ccd_2 : TIMER_CC2_CC_PWM_CFG_REG_s
cc_out_ccd_3 : TIMER_CC3_CC_PWM_CFG_REG_s
cc_out_ccu_0 : TIMER_CC0_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_REG_s
cc_out_ccu_1 : TIMER_CC1_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_REG_s
cc_out_ccu_2 : TIMER_CC2_CC_PWM_CFG_REG_s
cc_out_ccu_3 : TIMER_CC3_CC_PWM_CFG_REG_s
cc_out_fault_entry_0 : TIMER_CC0_CC_PWM_CFG_REG_s
cc_out_fault_entry_1 : TIMER_CC1_CC_PWM_CFG_REG_s
cc_out_fault_entry_2 : TIMER_CC2_CC_PWM_CFG_REG_s
cc_out_fault_entry_3 : TIMER_CC3_CC_PWM_CFG_REG_s
cc_out_fault_exit_0 : TIMER_CC0_CC_PWM_CFG_REG_s
cc_out_fault_exit_1 : TIMER_CC1_CC_PWM_CFG_REG_s
cc_out_fault_exit_2 : TIMER_CC2_CC_PWM_CFG_REG_s
cc_out_fault_exit_3 : TIMER_CC3_CC_PWM_CFG_REG_s
cc_out_inv_0 : TIMER_CC0_OUTPUT_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_OUTPUT_CTL_REG_s
cc_out_inv_1 : TIMER_CC1_OUTPUT_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_OUTPUT_CTL_REG_s
cc_out_inv_2 : TIMER_CC2_OUTPUT_CTL_REG_s
cc_out_inv_3 : TIMER_CC3_OUTPUT_CTL_REG_s
cc_out_load_0 : TIMER_CC0_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_REG_s
cc_out_load_1 : TIMER_CC1_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_REG_s
cc_out_load_2 : TIMER_CC2_CC_PWM_CFG_REG_s
cc_out_load_3 : TIMER_CC3_CC_PWM_CFG_REG_s
cc_out_sel_0 : TIMER_CC0_OUTPUT_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_OUTPUT_CTL_REG_s
cc_out_sel_1 : TIMER_CC1_OUTPUT_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_OUTPUT_CTL_REG_s
cc_out_sel_2 : TIMER_CC2_OUTPUT_CTL_REG_s
cc_out_sel_3 : TIMER_CC3_OUTPUT_CTL_REG_s
cc_out_sw_force_0 : TIMER_CC0_SW_FORCE_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_SW_FORCE_REG_s
cc_out_sw_force_1 : TIMER_CC1_SW_FORCE_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_SW_FORCE_REG_s
cc_out_sw_force_2 : TIMER_CC2_SW_FORCE_REG_s
cc_out_sw_force_3 : TIMER_CC3_SW_FORCE_REG_s
cc_out_val_init_0 : TIMER_CC0_OUTPUT_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_OUTPUT_CTL_REG_s
cc_out_val_init_1 : TIMER_CC1_OUTPUT_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_OUTPUT_CTL_REG_s
cc_out_val_init_2 : TIMER_CC2_OUTPUT_CTL_REG_s
cc_out_val_init_3 : TIMER_CC3_OUTPUT_CTL_REG_s
cc_out_zero_0 : TIMER_CC0_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_REG_s
cc_out_zero_1 : TIMER_CC1_CC_PWM_CFG_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_REG_s
cc_out_zero_2 : TIMER_CC2_CC_PWM_CFG_REG_s
cc_out_zero_3 : TIMER_CC3_CC_PWM_CFG_REG_s
ccact_update_method_0 : TIMER_CC0_COMPARE_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_COMPARE_CTRL_REG_s
ccact_update_method_1 : TIMER_CC1_COMPARE_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_COMPARE_CTRL_REG_s
ccact_update_method_2 : TIMER_CC2_COMPARE_CTRL_REG_s
ccact_update_method_3 : TIMER_CC3_COMPARE_CTRL_REG_s
ccd_0 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccd_0_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccd_0_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccd_0_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccd_0_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccd_0_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccd_1 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccd_1_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccd_1_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccd_1_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccd_1_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccd_1_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccd_2 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccd_2_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccd_2_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccd_2_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccd_2_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccd_2_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccd_3 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccd_3_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccd_3_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccd_3_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccd_3_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccd_3_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccd_4 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccd_4_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccd_4_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccd_4_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccd_4_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccd_4_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccd_5 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccd_5_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccd_5_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccd_5_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccd_5_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccd_5_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccd_act : timer_pwm_output_channel_action_cfg_t
CCR : SCB_Type
ccu_0 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccu_0_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccu_0_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccu_0_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccu_0_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccu_0_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccu_1 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccu_1_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccu_1_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccu_1_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccu_1_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccu_1_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccu_2 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccu_2_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccu_2_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccu_2_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccu_2_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccu_2_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccu_3 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccu_3_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccu_3_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccu_3_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccu_3_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccu_3_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccu_4 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccu_4_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccu_4_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccu_4_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccu_4_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccu_4_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccu_5 : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ccu_5_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ccu_5_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ccu_5_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ccu_5_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ccu_5_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
ccu_act : timer_pwm_output_channel_action_cfg_t
CFG : UART_REGS_s
cfg0 : COMP_SPARE_CTRL_REG_s, DAC_SPARE_CTRL_REG_s, I2C_SPARE_CTRL_REG_s, MCU_CTRL_SPARE_CTRL_REG_s, OPAMP_SPARE_CTRL_REG_s, SPI_SPARE_CTRL_REG_s
cfg1 : COMP_SPARE_CTRL_REG_s, DAC_SPARE_CTRL_REG_s, I2C_SPARE_CTRL_REG_s, MCU_CTRL_SPARE_CTRL_REG_s, OPAMP_SPARE_CTRL_REG_s, SPI_SPARE_CTRL_REG_s
CFG_0 : DMA_REGS_s
CFG_1 : DMA_REGS_s
CFG_2 : DMA_REGS_s
chan_id0 : DAC_EVENT_CTRL_REG_s, TIMER_EVENT_CTRL_REG_s
chan_id1 : TIMER_EVENT_CTRL_REG_s
chan_num : timer_pwm_cfg_t
channel_sel : ADC_CHNL_CFG_REG_s, adc_chnl_cfg_s
CHNL_CFG : ADC_REGS_s
CHNL_ENABLE_CLR : PL230_REGS_s
chnl_enable_clr : PL230_CHNL_ENABLE_CLR_REG_s
CHNL_ENABLE_SET : PL230_REGS_s
chnl_enable_set : PL230_CHNL_ENABLE_SET_REG_s
CHNL_PRI_ALT_CLR : PL230_REGS_s
chnl_pri_alt_clr : PL230_CHNL_PRI_ALT_CLR_REG_s
CHNL_PRI_ALT_SET : PL230_REGS_s
chnl_pri_alt_set : PL230_CHNL_PRI_ALT_SET_REG_s
CHNL_PRIORITY_CLR : PL230_REGS_s
chnl_priority_clr : PL230_CHNL_PRIORITY_CLR_REG_s
CHNL_PRIORITY_SET : PL230_REGS_s
chnl_priority_set : PL230_CHNL_PRIORITY_SET_REG_s
chnl_prot_ctrl : PL230_DMA_CFG_REG_s
CHNL_REQ_MASK_CLR : PL230_REGS_s
chnl_req_mask_clr : PL230_CHNL_REQ_MASK_CLR_REG_s
CHNL_REQ_MASK_SET : PL230_REGS_s
chnl_req_mask_set : PL230_CHNL_REQ_MASK_SET_REG_s
CHNL_SW_REQUEST : PL230_REGS_s
chnl_sw_request : PL230_CHNL_SW_REQUEST_REG_s
CHNL_USEBURST_CLR : PL230_REGS_s
chnl_useburst_clr : PL230_CHNL_USEBURST_CLR_REG_s
CHNL_USEBURST_SET : PL230_REGS_s
chnl_useburst_set : PL230_CHNL_USEBURST_SET_REG_s
chnls_minus1 : PL230_DMA_STATUS_REG_s
chnls_minus_1 : DMA_CFG_2_REG_s
chop_en : OPAMP_GAIN_CTRL0_REG_s
chop_mode : OPAMP_GAIN_CTRL0_REG_s
clen : FLASH_CTRL_REG_s
clk_32mhz_req : MCU_CTRL_INTR_EVENT_REG_s
clk_32mhz_req_en : MCU_CTRL_INTR_EN_REG_s
CLK_4MHZ_CTRL : MCU_CTRL_REGS_s
clk_4mhz_en : MCU_CTRL_CLK_4MHZ_CTRL_REG_s
clk_4mhz_ovrd_en : MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
clk_4mhz_ovrd_val : MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
clk_ahb_ovrd_en : MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
clk_ahb_ovrd_val : MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
clk_apb_ovrd_en : MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
clk_apb_ovrd_val : MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
clk_cal_ppm_val : RTC_RTC_CAL_REG_s
clk_cal_sign : RTC_RTC_CAL_REG_s
CLK_CONFIG : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CLK_CONFIG_u, TIMER_TIMG_NUM_INPUT2_REGS_s
clk_cpu_ovrd_en : MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
clk_cpu_ovrd_val : MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
CLK_CTRL : ADC_REGS_s, COMP_REGS_s, DAC_REGS_s, DMA_REGS_s, EVENT_FABRIC_REGS_s, FLASH_REGS_s, GPIO_REGS_s, I2C_REGS_s, MCU_CTRL_REGS_s, RTC_REGS_s, SPI_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CLK_CTRL_u, TIMER_TIMG_NUM_INPUT2_REGS_s, UART_REGS_s, VREF_REGS_s
CLK_DIV : SPI_REGS_s, UART_REGS_s
clk_div : adc_clk_cfg_s, ADC_CLK_CTRL_REG_s, timer_clk_cfg_t, TIMER_CLK_CONFIG_REG_s, TIMER_TIMG_NUM_INPUT2_CLK_CONFIG_REG_s, uart_cfg_s, UART_CLK_DIV_REG_s, VREF_CLK_CTRL_REG_s, WATCHDOG_WWDT_CTL0_REG_s
clk_en : adc_clk_cfg_s, ADC_CLK_CTRL_REG_s, DAC_CLK_CTRL_REG_s, DMA_CLK_CTRL_REG_s, EVENT_FABRIC_CLK_CTRL_REG_s, FLASH_CLK_CTRL_REG_s, MCU_CTRL_CLK_CTRL_REG_s, RTC_CLK_CTRL_REG_s, TIMER_CLK_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CLK_CTRL_REG_s, UART_CLK_CTRL_REG_s
clk_freq : uart_cfg_s
clk_lf_mon_fault : MCU_CTRL_INTR_EVENT_REG_s
clk_lf_mon_fault_en : MCU_CTRL_INTR_EN_REG_s
clk_lf_ovrd_en : MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
clk_lf_ovrd_val : MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
clk_phase : spi_cfg_t
clk_polarity : spi_cfg_t
CLK_PWR_EN : MCU_CTRL_REGS_s
clk_scaler : SPI_CLK_CTRL_REG_s
CLK_SEL : ADC_REGS_s, UART_REGS_s
clk_sel : adc_clk_cfg_s, ADC_CLK_SEL_REG_s, SPI_CLKSEL_REG_s, timer_clk_cfg_t, TIMER_CLK_CONFIG_REG_s, TIMER_TIMG_NUM_INPUT2_CLK_CONFIG_REG_s, uart_cfg_s, UART_CLK_SEL_REG_s, VREF_CLK_CTRL_REG_s
CLKCFG : UART_REGS_s
clkdiv : I2C_CLK_CTRL_REG_s
CLKSEL : SPI_REGS_s
clksel : I2C_CLK_CTRL_REG_s
clkstretch_timeout : I2C_INTR_EVENT_REG_s
clkstretch_timeout_en : I2C_INTR_EN_0_REG_s
clkstretch_timeout_nmi_en : I2C_INTR_NMI_EN_0_REG_s
clkstretch_timeout_sw_set : I2C_INTR_SW_SET_0_REG_s
clock_phase : SPI_MOT_MOD_CNTRL_REG_s
clock_polarity : SPI_MOT_MOD_CNTRL_REG_s
closed_window : WATCHDOG_WWDT_CTL0_REG_s
cmd : VULTAN_FLASH_CTRL_REG_s
cmd_accept : VULTAN_FLASH_STATUS_REG_s
cmd_accept_irq : VULTAN_FLASH_IRQ_MASKED_STATUS_REG_s
cmd_accept_irq_en_clr : VULTAN_FLASH_IRQ_ENABLE_CLR_REG_s
cmd_accept_irq_en_set : VULTAN_FLASH_IRQ_ENABLE_SET_REG_s
cmd_accept_irq_sts_clr : VULTAN_FLASH_IRQ_STATUS_CLR_REG_s
cmd_accept_irq_sts_set : VULTAN_FLASH_IRQ_STATUS_SET_REG_s
CMD_DATA_CTRL : SPI_REGS_s
cmd_data_mode_en : SPI_CMD_DATA_CTRL_REG_s
cmd_data_mode_val : SPI_CMD_DATA_CTRL_REG_s
cmd_fail : VULTAN_FLASH_STATUS_REG_s
cmd_fail_irq : VULTAN_FLASH_IRQ_MASKED_STATUS_REG_s
cmd_fail_irq_en_clr : VULTAN_FLASH_IRQ_ENABLE_CLR_REG_s
cmd_fail_irq_en_set : VULTAN_FLASH_IRQ_ENABLE_SET_REG_s
cmd_fail_irq_sts_clr : VULTAN_FLASH_IRQ_STATUS_CLR_REG_s
cmd_fail_irq_sts_set : VULTAN_FLASH_IRQ_STATUS_SET_REG_s
cmd_finish : VULTAN_FLASH_STATUS_REG_s
cmd_pending : VULTAN_FLASH_STATUS_REG_s
cmd_reject_irq : VULTAN_FLASH_IRQ_MASKED_STATUS_REG_s
cmd_reject_irq_en_clr : VULTAN_FLASH_IRQ_ENABLE_CLR_REG_s
cmd_reject_irq_en_set : VULTAN_FLASH_IRQ_ENABLE_SET_REG_s
cmd_reject_irq_sts_clr : VULTAN_FLASH_IRQ_STATUS_CLR_REG_s
cmd_reject_irq_sts_set : VULTAN_FLASH_IRQ_STATUS_SET_REG_s
cmd_success : VULTAN_FLASH_STATUS_REG_s
cmd_success_irq : VULTAN_FLASH_IRQ_MASKED_STATUS_REG_s
cmd_success_irq_en_clr : VULTAN_FLASH_IRQ_ENABLE_CLR_REG_s
cmd_success_irq_en_set : VULTAN_FLASH_IRQ_ENABLE_SET_REG_s
cmd_success_irq_sts_clr : VULTAN_FLASH_IRQ_STATUS_CLR_REG_s
cmd_success_irq_sts_set : VULTAN_FLASH_IRQ_STATUS_SET_REG_s
COMP_CLK_CTRL_REG_s : COMP_CLK_CTRL_u
COMP_CTRL0_REG_s : COMP_CTRL0_u
COMP_DESC_REG_s : COMP_DESC_u
COMP_EVENT_EN_REG_s : COMP_EVENT_EN_u
COMP_INPUT_CTRL0_REG_s : COMP_INPUT_CTRL0_u
COMP_INPUT_CTRL1_REG_s : COMP_INPUT_CTRL1_u
COMP_INTR_EN_REG_s : COMP_INTR_EN_u
COMP_INTR_EVENT_REG_s : COMP_INTR_EVENT_u
COMP_INTR_NMI_EN_REG_s : COMP_INTR_NMI_EN_u
COMP_INTR_STS_REG_s : COMP_INTR_STS_u
COMP_INTR_SW_SET_REG_s : COMP_INTR_SW_SET_u
comp_out : COMP_INTR_EVENT_REG_s
COMP_OUT_CTRL0_REG_s : COMP_OUT_CTRL0_u
COMP_OUT_CTRL1_REG_s : COMP_OUT_CTRL1_u
comp_out_edge0 : COMP_INTR_EVENT_REG_s
comp_out_edge0_en : COMP_INTR_EN_REG_s
comp_out_edge0_event_en : COMP_EVENT_EN_REG_s
comp_out_edge0_nmi_en : COMP_INTR_NMI_EN_REG_s
comp_out_edge0_sw_set : COMP_INTR_SW_SET_REG_s
comp_out_edge1 : COMP_INTR_EVENT_REG_s
comp_out_edge1_en : COMP_INTR_EN_REG_s
comp_out_edge1_event_en : COMP_EVENT_EN_REG_s
comp_out_edge1_nmi_en : COMP_INTR_NMI_EN_REG_s
comp_out_edge1_sw_set : COMP_INTR_SW_SET_REG_s
comp_out_en : COMP_INTR_EN_REG_s
comp_out_event_en : COMP_EVENT_EN_REG_s
comp_out_nmi_en : COMP_INTR_NMI_EN_REG_s
comp_out_sts : COMP_STS_REG_s
comp_out_sw_set : COMP_INTR_SW_SET_REG_s
COMP_PWR_EN_REG_s : COMP_PWR_EN_u
COMP_REF_CTRL0_REG_s : COMP_REF_CTRL0_u
COMP_REF_CTRL1_REG_s : COMP_REF_CTRL1_u
COMP_RST_CTRL_REG_s : COMP_RST_CTRL_u
COMP_RST_STS_REG_s : COMP_RST_STS_u
COMP_SPARE_CTRL_REG_s : COMP_SPARE_CTRL_u
COMP_SPARE_STS_REG_s : COMP_SPARE_STS_u
COMP_STS_REG_s : COMP_STS_u
comp_val_0 : TIMER_CC0_COMPARE_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_COMPARE_CTRL_REG_s
comp_val_1 : TIMER_CC1_COMPARE_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_COMPARE_CTRL_REG_s
comp_val_2 : TIMER_CC2_COMPARE_CTRL_REG_s
comp_val_3 : TIMER_CC3_COMPARE_CTRL_REG_s
comp_val_4 : TIMER_CC4_COMPARE_CTRL_REG_s
comp_val_5 : TIMER_CC5_COMPARE_CTRL_REG_s
comp_val_update_method_0 : TIMER_CC0_COMPARE_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_COMPARE_CTRL_REG_s
comp_val_update_method_1 : TIMER_CC1_COMPARE_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_COMPARE_CTRL_REG_s
comp_val_update_method_2 : TIMER_CC2_COMPARE_CTRL_REG_s
comp_val_update_method_3 : TIMER_CC3_COMPARE_CTRL_REG_s
comp_val_update_method_4 : TIMER_CC4_COMPARE_CTRL_REG_s
comp_val_update_method_5 : TIMER_CC5_COMPARE_CTRL_REG_s
control_base_ptr : PL230_CTRL_BASE_PTR_REG_s
CONV_CFG : ADC_REGS_s
conv_mode : ADC_CONV_CFG_REG_s
conv_time : adc_timer_cfg_s
count_mode : TIMER_CTR_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CTR_CTL_REG_s
cpecc : FLASH_CTRL_REG_s
CPUID : SCB_Type
CRC_CRCCONFIG_REG_s : CRC_CRCCONFIG_u
CRC_CRCINPUT_REG_s : CRC_CRCINPUT_u
CRC_CRCRESULT_REG_s : CRC_CRCRESULT_u
CRC_CRCSEED_REG_s : CRC_CRCSEED_u
CRC_OUT_BYTE : I2C_REGS_s
CRC_PWR_EN_REG_s : CRC_PWR_EN_u
CRC_RST_CTRL_REG_s : CRC_RST_CTRL_u
CRC_RST_STS_REG_s : CRC_RST_STS_u
CRCCONFIG : CRC_REGS_s
CRCINPUT : CRC_REGS_s
CRCRESULT : CRC_REGS_s
CRCSEED : CRC_REGS_s
CS_CTRL : SPI_REGS_s
cs_hold_cnt : SPI_CS_SETUP_HOLD_CNT_REG_s
cs_sel : SPI_CS_CTRL_REG_s
cs_setup_cnt : SPI_CS_SETUP_HOLD_CNT_REG_s
CS_SETUP_HOLD_CNT : SPI_REGS_s
ctr_adv_cond : timer_ctr_cfg_t
ctr_adv_ctrl : TIMER_CTR_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CTR_CTL_REG_s
ctr_after_debug : TIMER_CTR_CTL_REG_s
ctr_cfg : timer_pwm_cfg_t
CTR_CTL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CTR_CTL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
ctr_during_fault : TIMER_CTR_CTL_REG_s
ctr_en : TIMER_CTR_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CTR_CTL_REG_s
ctr_en_during_debug : RTC_DEBUG_CTL_REG_s
ctr_exit_fault : TIMER_CTR_CTL_REG_s
ctr_load : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ctr_load_cond : timer_ctr_cfg_t
ctr_load_ctrl : TIMER_CTR_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CTR_CTL_REG_s
ctr_load_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ctr_load_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ctr_load_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ctr_load_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ctr_load_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
CTR_LOAD_VAL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CTR_LOAD_VAL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
ctr_load_val : TIMER_CTR_LOAD_VAL_REG_s, TIMER_TIMG_NUM_INPUT2_CTR_LOAD_VAL_REG_s
ctr_mode : timer_ctr_cfg_t
CTR_PL_VAL : TIMER_REGS_s
CTR_VAL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_CTR_VAL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
ctr_val : TIMER_CTR_VAL_REG_s, TIMER_TIMG_NUM_INPUT2_CTR_VAL_REG_s
ctr_zero : TIMER_INTR_EVENT_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
ctr_zero_cond : timer_ctr_cfg_t
ctr_zero_ctrl : TIMER_CTR_CTL_REG_s, TIMER_TIMG_NUM_INPUT2_CTR_CTL_REG_s
ctr_zero_en : TIMER_INTR_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
ctr_zero_event_en_0 : TIMER_EVENT_EN_0_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
ctr_zero_event_en_1 : TIMER_EVENT_EN_1_0_REG_s, TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
ctr_zero_nmi_en : TIMER_INTR_NMI_EN_0_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
ctr_zero_sw_set : TIMER_INTR_SW_SET_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
CTRL : FLASH_REGS_s, SysTick_Type, UART_REGS_s, VREF_REGS_s, VULTAN_FLASH_REGS_s
ctrl : dma_mem_channel_cfg_t
CTRL0 : COMP_REGS_s, DAC_REGS_s, OPAMP_REGS_s
CTRL1 : DAC_REGS_s
CTRL2 : DAC_REGS_s
CTRL3 : DAC_REGS_s
CTRL_BASE_PTR : PL230_REGS_s
ctrl_base_ptr : DMA_CFG_0_REG_s
cts_en : uart_cfg_s, UART_CTRL_REG_s
cts_int : UART_INTR_EVENT_REG_s
cts_int_en : UART_INTR_EN1_REG_s
cts_int_nmi_en : UART_INTR_NMI_EN1_REG_s
cts_int_sw_set : UART_INTR_SW_SET_REG_s
cts_sts : UART_STS_REG_s
curr_state : ADC_SM_STATE_REG_s
cycle_ctrl : dma_mem_ctrl_cfg_t