FD32M0P Microcontroller SDK
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Data Structures
Here are the data structures with brief descriptions:
C
ADC_BLOCK_ASYNC_REQ_REG_s
C
ADC_BLOCK_ASYNC_REQ_u
C
ADC_CALIBRATION_REQ_REG_s
C
ADC_CALIBRATION_REQ_u
C
ADC_CHNL_CFG_REG_s
C
adc_chnl_cfg_s
ADC Channel Configuration Struct
C
ADC_CHNL_CFG_u
C
adc_clk_cfg_s
ADC Clock Configuration Struct
C
ADC_CLK_CTRL_REG_s
C
ADC_CLK_CTRL_u
C
ADC_CLK_SEL_REG_s
C
ADC_CLK_SEL_u
C
ADC_CONV_CFG_REG_s
C
ADC_CONV_CFG_u
C
ADC_DBG_CTRL_REG_s
C
ADC_DBG_CTRL_u
C
ADC_DESC_REG_s
C
ADC_DESC_u
C
adc_dma_cfg_s
ADC DMA Configuration Struct
C
ADC_DMA_EVENT_EN_0_REG_s
C
ADC_DMA_EVENT_EN_0_u
C
ADC_DMA_EVENT_EN_1_REG_s
C
ADC_DMA_EVENT_EN_1_u
C
ADC_DMA_REG_REG_s
C
ADC_DMA_REG_u
C
ADC_DMA_TRANSFER_CNT_REG_s
C
ADC_DMA_TRANSFER_CNT_u
C
ADC_EOC_ANA_REG_s
C
ADC_EOC_ANA_u
C
ADC_EVENT_EN_0_REG_s
C
ADC_EVENT_EN_0_u
C
ADC_EVENT_EN_1_REG_s
C
ADC_EVENT_EN_1_u
C
ADC_HW_AVG_CFG_REG_s
C
adc_hw_avg_cfg_s
ADC Hardware Averaging Configuration Struct
C
ADC_HW_AVG_CFG_u
C
ADC_INTR_EN_0_REG_s
C
ADC_INTR_EN_0_u
C
ADC_INTR_EN_1_REG_s
C
ADC_INTR_EN_1_u
C
ADC_INTR_EVENT_REG_s
C
ADC_INTR_EVENT_u
C
ADC_INTR_NMI_EN_0_REG_s
C
ADC_INTR_NMI_EN_0_u
C
ADC_INTR_NMI_EN_1_REG_s
C
ADC_INTR_NMI_EN_1_u
C
ADC_INTR_STS_REG_s
C
ADC_INTR_STS_u
C
ADC_INTR_SW_REG_s
C
ADC_INTR_SW_u
C
adc_multi_ch_conv_cfg_s
ADC Multi Channel Conv Configuration Struct
C
ADC_POWER_DN_REG_s
C
ADC_POWER_DN_u
C
ADC_PUBS_PORT_REG_s
C
ADC_PUBS_PORT_u
C
ADC_PWR_EN_REG_s
C
ADC_PWR_EN_u
C
ADC_REGS_s
C
ADC_RESULT_CFG_REG_s
C
ADC_RESULT_CFG_u
C
ADC_RESULT_REG_s
C
ADC_RESULT_u
C
ADC_RST_CTRL_REG_s
C
ADC_RST_CTRL_u
C
ADC_RST_STS_REG_s
C
ADC_RST_STS_u
C
adc_samp_timer_cfg_s
ADC Sampling Timer Struct
C
adc_single_ch_conv_cfg_s
ADC Single Channel Conv Configuration Struct
C
ADC_SM_STATE_REG_s
C
ADC_SM_STATE_u
C
ADC_SPARE_CTRL_REG_s
C
ADC_SPARE_CTRL_u
C
ADC_SPARE_STS_REG_s
C
ADC_SPARE_STS_u
C
ADC_STATUS_REG_s
C
ADC_STATUS_u
C
ADC_SUBS_PORT_REG_s
C
ADC_SUBS_PORT_u
C
adc_sw_trig_cfg_s
ADC Software Trigger Struct
C
ADC_SW_TRIGGER_REG_s
C
ADC_SW_TRIGGER_u
C
adc_temp_cfg_s
ADC Temperature Configuration Struct
C
ADC_TEMP_SENSOR_EN_REG_s
C
ADC_TEMP_SENSOR_EN_u
C
adc_timer_cfg_s
ADC Timer Configuration Struct
C
ADC_TIMER_CONVERSION_REG_s
C
ADC_TIMER_CONVERSION_u
C
ADC_TIMER_SAMPLE_REG_s
C
ADC_TIMER_SAMPLE_u
C
ADC_TIMER_START_REG_s
C
ADC_TIMER_START_u
C
ADC_WINDOW_COMP_REG_s
C
ADC_WINDOW_COMP_u
C
APSR_Type
Union type to access the Application Program Status Register (APSR)
C
APSR_Type.b
C
BOOTLOADER_BCR_CFG0_REG_s
C
BOOTLOADER_BCR_CFG0_u
C
BOOTLOADER_BCR_CFG1_REG_s
C
BOOTLOADER_BCR_CFG1_u
C
BOOTLOADER_BCR_CFG2_REG_s
C
BOOTLOADER_BCR_CFG2_u
C
BOOTLOADER_BCR_CONFIG_ID_REG_s
C
BOOTLOADER_BCR_CONFIG_ID_u
C
BOOTLOADER_BCR_CRCCFG0_REG_s
C
BOOTLOADER_BCR_CRCCFG0_u
C
BOOTLOADER_BCR_CRCCFG1_REG_s
C
BOOTLOADER_BCR_CRCCFG1_u
C
BOOTLOADER_BCR_CRCCFG2_REG_s
C
BOOTLOADER_BCR_CRCCFG2_u
C
BOOTLOADER_BCR_CRCCFG3_REG_s
C
BOOTLOADER_BCR_CRCCFG3_u
C
BOOTLOADER_BCR_FLASH_WP_REG_s
C
BOOTLOADER_BCR_FLASH_WP_u
C
BOOTLOADER_BSL_CONFIG_ID_REG_s
C
BOOTLOADER_BSL_CONFIG_ID_u
C
BOOTLOADER_BSL_I2C_CFG_REG_s
C
BOOTLOADER_BSL_I2C_CFG_u
C
BOOTLOADER_BSL_PWD_REG_s
C
BOOTLOADER_BSL_PWD_u
C
BOOTLOADER_BSL_UART_CFG0_REG_s
C
BOOTLOADER_BSL_UART_CFG0_u
C
BOOTLOADER_BSL_UART_CFG1_REG_s
C
BOOTLOADER_BSL_UART_CFG1_u
C
BOOTLOADER_REGS_s
C
comp_cfg_s
COMP Configuration Struct
C
COMP_CLK_CTRL_REG_s
C
COMP_CLK_CTRL_u
C
COMP_CTRL0_REG_s
C
COMP_CTRL0_u
C
COMP_DESC_REG_s
C
COMP_DESC_u
C
COMP_EVENT_EN_REG_s
C
COMP_EVENT_EN_u
C
COMP_INPUT_CTRL0_REG_s
C
COMP_INPUT_CTRL0_u
C
COMP_INPUT_CTRL1_REG_s
C
COMP_INPUT_CTRL1_u
C
COMP_INTR_EN_REG_s
C
COMP_INTR_EN_u
C
COMP_INTR_EVENT_REG_s
C
COMP_INTR_EVENT_u
C
COMP_INTR_NMI_EN_REG_s
C
COMP_INTR_NMI_EN_u
C
COMP_INTR_STS_REG_s
C
COMP_INTR_STS_u
C
COMP_INTR_SW_SET_REG_s
C
COMP_INTR_SW_SET_u
C
comp_out_cfg_s
C
COMP_OUT_CTRL0_REG_s
C
COMP_OUT_CTRL0_u
C
COMP_OUT_CTRL1_REG_s
C
COMP_OUT_CTRL1_u
C
COMP_PWR_EN_REG_s
C
COMP_PWR_EN_u
C
COMP_REF_CTRL0_REG_s
C
COMP_REF_CTRL0_u
C
COMP_REF_CTRL1_REG_s
C
COMP_REF_CTRL1_u
C
COMP_REGS_s
C
COMP_RST_CTRL_REG_s
C
COMP_RST_CTRL_u
C
COMP_RST_STS_REG_s
C
COMP_RST_STS_u
C
COMP_SPARE_CTRL_REG_s
C
COMP_SPARE_CTRL_u
C
COMP_SPARE_STS_REG_s
C
COMP_SPARE_STS_u
C
COMP_STS_REG_s
C
COMP_STS_u
C
comp_win_comp_cfg_s
C
CONTROL_Type
Union type to access the Control Registers (CONTROL)
C
CONTROL_Type.b
C
CoreSightPart
C
crc_cfg_s
CRC Configuration Struct
C
CRC_CRCCONFIG_REG_s
C
CRC_CRCCONFIG_u
C
CRC_CRCINPUT_REG_s
C
CRC_CRCINPUT_u
C
CRC_CRCRESULT_REG_s
C
CRC_CRCRESULT_u
C
CRC_CRCSEED_REG_s
C
CRC_CRCSEED_u
C
CRC_PWR_EN_REG_s
C
CRC_PWR_EN_u
C
CRC_REGS_s
C
CRC_RST_CTRL_REG_s
C
CRC_RST_CTRL_u
C
CRC_RST_STS_REG_s
C
CRC_RST_STS_u
C
DAC_CAL_CTRL_REG_s
C
DAC_CAL_CTRL_u
C
DAC_CAL_STS_REG_s
C
DAC_CAL_STS_u
C
dac_cfg_s
DAC Configuration Struct
C
DAC_CLK_CTRL_REG_s
C
DAC_CLK_CTRL_u
C
DAC_CTRL0_REG_s
C
DAC_CTRL0_u
C
DAC_CTRL1_REG_s
C
DAC_CTRL1_u
C
DAC_CTRL2_REG_s
C
DAC_CTRL2_u
C
DAC_CTRL3_REG_s
C
DAC_CTRL3_u
C
DAC_DATA_REG_s
C
DAC_DATA_u
C
DAC_DESC_REG_s
C
DAC_DESC_u
C
dac_dma_cfg_s
DAC DMA Configuration Struct
C
DAC_EVENT_CTRL_REG_s
C
DAC_EVENT_CTRL_u
C
DAC_EVENT_EN_REG_s
C
DAC_EVENT_EN_u
C
DAC_INTR_EN_REG_s
C
DAC_INTR_EN_u
C
DAC_INTR_EVENT_REG_s
C
DAC_INTR_EVENT_u
C
DAC_INTR_NMI_EN_REG_s
C
DAC_INTR_NMI_EN_u
C
DAC_INTR_STS_REG_s
C
DAC_INTR_STS_u
C
DAC_INTR_SW_SET_REG_s
C
DAC_INTR_SW_SET_u
C
DAC_PWR_EN_REG_s
C
DAC_PWR_EN_u
C
DAC_REGS_s
C
DAC_RST_CTRL_REG_s
C
DAC_RST_CTRL_u
C
DAC_RST_STS_REG_s
C
DAC_RST_STS_u
C
DAC_SPARE_CTRL_REG_s
C
DAC_SPARE_CTRL_u
C
DAC_SPARE_STS_REG_s
C
DAC_SPARE_STS_u
C
DMA_ARBITRATION_MASK_REG_s
C
DMA_ARBITRATION_MASK_u
C
DMA_ARBITRATION_REG_s
C
DMA_ARBITRATION_u
C
DMA_CFG_0_REG_s
C
DMA_CFG_0_u
C
DMA_CFG_1_REG_s
C
DMA_CFG_1_u
C
DMA_CFG_2_REG_s
C
DMA_CFG_2_u
C
dma_channel_cfg_t
Channel based transfer configuration
C
DMA_CLK_CTRL_REG_s
C
DMA_CLK_CTRL_u
C
DMA_DBG_CTRL_REG_s
C
DMA_DBG_CTRL_u
C
DMA_DESC_REG_s
C
DMA_DESC_u
C
DMA_EARLY_IRQ_0_REG_s
C
DMA_EARLY_IRQ_0_u
C
DMA_EARLY_IRQ_10_REG_s
C
DMA_EARLY_IRQ_10_u
C
DMA_EARLY_IRQ_11_REG_s
C
DMA_EARLY_IRQ_11_u
C
DMA_EARLY_IRQ_12_REG_s
C
DMA_EARLY_IRQ_12_u
C
DMA_EARLY_IRQ_13_REG_s
C
DMA_EARLY_IRQ_13_u
C
DMA_EARLY_IRQ_14_REG_s
C
DMA_EARLY_IRQ_14_u
C
DMA_EARLY_IRQ_15_REG_s
C
DMA_EARLY_IRQ_15_u
C
DMA_EARLY_IRQ_1_REG_s
C
DMA_EARLY_IRQ_1_u
C
DMA_EARLY_IRQ_2_REG_s
C
DMA_EARLY_IRQ_2_u
C
DMA_EARLY_IRQ_3_REG_s
C
DMA_EARLY_IRQ_3_u
C
DMA_EARLY_IRQ_4_REG_s
C
DMA_EARLY_IRQ_4_u
C
DMA_EARLY_IRQ_5_REG_s
C
DMA_EARLY_IRQ_5_u
C
DMA_EARLY_IRQ_6_REG_s
C
DMA_EARLY_IRQ_6_u
C
DMA_EARLY_IRQ_7_REG_s
C
DMA_EARLY_IRQ_7_u
C
DMA_EARLY_IRQ_8_REG_s
C
DMA_EARLY_IRQ_8_u
C
DMA_EARLY_IRQ_9_REG_s
C
DMA_EARLY_IRQ_9_u
C
DMA_EARLY_IRQ_CFG_REG_s
C
DMA_EARLY_IRQ_CFG_u
C
DMA_EVENT_EN_0_REG_s
C
DMA_EVENT_EN_0_u
C
DMA_EVENT_EN_1_REG_s
C
DMA_EVENT_EN_1_u
C
DMA_FILL_MODE_CFG_REG_s
C
DMA_FILL_MODE_CFG_u
C
DMA_FILL_MODE_REG_s
C
DMA_FILL_MODE_u
C
DMA_INTR_EN_0_REG_s
C
DMA_INTR_EN_0_u
C
DMA_INTR_EN_1_REG_s
C
DMA_INTR_EN_1_u
C
DMA_INTR_EVENT_REG_s
C
DMA_INTR_EVENT_u
C
DMA_INTR_NMI_EN_0_REG_s
C
DMA_INTR_NMI_EN_0_u
C
DMA_INTR_NMI_EN_1_REG_s
C
DMA_INTR_NMI_EN_1_u
C
DMA_INTR_STS_REG_s
C
DMA_INTR_STS_u
C
DMA_INTR_SW_SET_REG_s
C
DMA_INTR_SW_SET_u
C
dma_mem_channel_cfg_t
Channel Configuration struct
C
dma_mem_ctrl_cfg_t
Channel Control Configuration Struct
C
DMA_PWR_EN_REG_s
C
DMA_PWR_EN_u
C
DMA_REGS_s
C
DMA_REPEATED_TRANSFER_ALTERNATE_SEL_REG_s
C
DMA_REPEATED_TRANSFER_ALTERNATE_SEL_u
C
DMA_REPEATED_TRANSFER_CHNL_0_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_0_u
C
DMA_REPEATED_TRANSFER_CHNL_10_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_10_u
C
DMA_REPEATED_TRANSFER_CHNL_11_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_11_u
C
DMA_REPEATED_TRANSFER_CHNL_12_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_12_u
C
DMA_REPEATED_TRANSFER_CHNL_13_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_13_u
C
DMA_REPEATED_TRANSFER_CHNL_14_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_14_u
C
DMA_REPEATED_TRANSFER_CHNL_15_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_15_u
C
DMA_REPEATED_TRANSFER_CHNL_1_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_1_u
C
DMA_REPEATED_TRANSFER_CHNL_2_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_2_u
C
DMA_REPEATED_TRANSFER_CHNL_3_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_3_u
C
DMA_REPEATED_TRANSFER_CHNL_4_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_4_u
C
DMA_REPEATED_TRANSFER_CHNL_5_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_5_u
C
DMA_REPEATED_TRANSFER_CHNL_6_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_6_u
C
DMA_REPEATED_TRANSFER_CHNL_7_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_7_u
C
DMA_REPEATED_TRANSFER_CHNL_8_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_8_u
C
DMA_REPEATED_TRANSFER_CHNL_9_REG_s
C
DMA_REPEATED_TRANSFER_CHNL_9_u
C
DMA_REPEATED_TRANSFER_EN_REG_s
C
DMA_REPEATED_TRANSFER_EN_u
C
DMA_RST_CTRL_REG_s
C
DMA_RST_CTRL_u
C
DMA_RST_STS_REG_s
C
DMA_RST_STS_u
C
DMA_STRIDE_MODE_CFG_0_REG_s
C
DMA_STRIDE_MODE_CFG_0_u
C
DMA_STRIDE_MODE_CFG_1_REG_s
C
DMA_STRIDE_MODE_CFG_1_u
C
DMA_STRIDE_MODE_CFG_2_REG_s
C
DMA_STRIDE_MODE_CFG_2_u
C
DMA_STRIDE_MODE_REG_s
C
DMA_STRIDE_MODE_u
C
DMA_WAITONREQ_REG_s
C
DMA_WAITONREQ_u
C
eeprom_block_t
This struct is used to access EEPROM Reads. @Note Even if the size of each mem in the struct is Halfword, each eeprom location is byte
C
event_fabric_chnl_cfg
Event Fabric Channel Configuration Struct
C
EVENT_FABRIC_CLK_CTRL_REG_s
C
EVENT_FABRIC_CLK_CTRL_u
C
EVENT_FABRIC_DESC_REG_s
C
EVENT_FABRIC_DESC_u
C
EVENT_FABRIC_DMA_PUB_REG_s
C
EVENT_FABRIC_DMA_PUB_u
C
EVENT_FABRIC_GEN_PUB_REG_s
C
EVENT_FABRIC_GEN_PUB_u
C
EVENT_FABRIC_GEN_SUB_REG_s
C
EVENT_FABRIC_GEN_SUB_u
C
EVENT_FABRIC_PWR_EN_REG_s
C
EVENT_FABRIC_PWR_EN_u
C
EVENT_FABRIC_REGS_s
C
EVENT_FABRIC_RST_CTRL_REG_s
C
EVENT_FABRIC_RST_CTRL_u
C
EVENT_FABRIC_RST_STS_REG_s
C
EVENT_FABRIC_RST_STS_u
C
FLASH_CLK_CTRL_REG_s
C
FLASH_CLK_CTRL_u
C
FLASH_CTRL_REG_s
C
FLASH_CTRL_u
C
FLASH_DESC_REG_s
C
FLASH_DESC_u
C
FLASH_ECED_STATUS_REG_s
C
FLASH_ECED_STATUS_u
C
FLASH_HSIZE_CTRL_REG_s
C
FLASH_HSIZE_CTRL_u
C
FLASH_REGS_s
C
FLASH_STATUS_REG_s
C
FLASH_STATUS_u
C
FLASH_STS_REG_s
C
FLASH_STS_u
C
FLASH_TIME_CTRL_1_REG_s
C
FLASH_TIME_CTRL_1_u
C
FLASH_TIME_CTRL_2_REG_s
C
FLASH_TIME_CTRL_2_u
C
FLASH_TIME_CTRL_REG_s
C
FLASH_TIME_CTRL_u
C
FLASH_TIME_UPTD_REG_s
C
FLASH_TIME_UPTD_u
C
flash_timing_regs_cfg_t
Struct for flash timing and mode of operations
C
GPIO_CLK_CTRL_REG_s
C
GPIO_CLK_CTRL_u
C
GPIO_DESC_REG_s
C
GPIO_DESC_u
C
GPIO_DIN_11_8_REG_s
C
GPIO_DIN_11_8_u
C
GPIO_DIN_15_12_REG_s
C
GPIO_DIN_15_12_u
C
GPIO_DIN_19_16_REG_s
C
GPIO_DIN_19_16_u
C
GPIO_DIN_23_20_REG_s
C
GPIO_DIN_23_20_u
C
GPIO_DIN_27_24_REG_s
C
GPIO_DIN_27_24_u
C
GPIO_DIN_31_28_REG_s
C
GPIO_DIN_31_28_u
C
GPIO_DIN_3_0_REG_s
C
GPIO_DIN_3_0_u
C
GPIO_DIN_7_4_REG_s
C
GPIO_DIN_7_4_u
C
GPIO_DIN_REG_s
C
GPIO_DIN_u
C
GPIO_DMA_WR_MASK_REG_s
C
GPIO_DMA_WR_MASK_u
C
GPIO_DOUT_11_8_REG_s
C
GPIO_DOUT_11_8_u
C
GPIO_DOUT_15_12_REG_s
C
GPIO_DOUT_15_12_u
C
GPIO_DOUT_19_16_REG_s
C
GPIO_DOUT_19_16_u
C
GPIO_DOUT_23_20_REG_s
C
GPIO_DOUT_23_20_u
C
GPIO_DOUT_27_24_REG_s
C
GPIO_DOUT_27_24_u
C
GPIO_DOUT_31_28_REG_s
C
GPIO_DOUT_31_28_u
C
GPIO_DOUT_3_0_REG_s
C
GPIO_DOUT_3_0_u
C
GPIO_DOUT_7_4_REG_s
C
GPIO_DOUT_7_4_u
C
GPIO_DOUT_CLR_REG_s
C
GPIO_DOUT_CLR_u
C
GPIO_DOUT_EN_CLR_REG_s
C
GPIO_DOUT_EN_CLR_u
C
GPIO_DOUT_EN_REG_s
C
GPIO_DOUT_EN_SET_REG_s
C
GPIO_DOUT_EN_SET_u
C
GPIO_DOUT_EN_u
C
GPIO_DOUT_REG_s
C
GPIO_DOUT_SET_REG_s
C
GPIO_DOUT_SET_u
C
GPIO_DOUT_TGL_REG_s
C
GPIO_DOUT_TGL_u
C
GPIO_DOUT_u
C
GPIO_EVENT_EN0_REG_s
C
GPIO_EVENT_EN0_u
C
GPIO_EVENT_EN1_REG_s
C
GPIO_EVENT_EN1_u
C
GPIO_FILT_EN_0_REG_s
C
GPIO_FILT_EN_0_u
C
GPIO_FILT_EN_1_REG_s
C
GPIO_FILT_EN_1_u
C
GPIO_INTR_EN0_REG_s
C
GPIO_INTR_EN0_u
C
GPIO_INTR_EN1_REG_s
C
GPIO_INTR_EN1_u
C
GPIO_INTR_EVENT_REG_s
C
GPIO_INTR_EVENT_u
C
GPIO_INTR_NMI_EN0_REG_s
C
GPIO_INTR_NMI_EN0_u
C
GPIO_INTR_NMI_EN1_REG_s
C
GPIO_INTR_NMI_EN1_u
C
GPIO_INTR_POL_0_REG_s
C
GPIO_INTR_POL_0_u
C
GPIO_INTR_POL_1_REG_s
C
GPIO_INTR_POL_1_u
C
GPIO_INTR_STS_REG_s
C
GPIO_INTR_STS_u
C
GPIO_INTR_SW_SET_REG_s
C
GPIO_INTR_SW_SET_u
C
GPIO_PWR_EN_REG_s
C
GPIO_PWR_EN_u
C
GPIO_REGS_s
C
GPIO_RST_CTRL_REG_s
C
GPIO_RST_CTRL_u
C
GPIO_RST_STS_REG_s
C
GPIO_RST_STS_u
C
GPIO_SUB_CFG_REG_s
C
GPIO_SUB_CFG_u
C
I2C_CLK_CTRL_REG_s
C
I2C_CLK_CTRL_u
C
i2c_counter_cfg_t
I2C Counter Configuration struct
C
I2C_CRC_OUT_BYTE_REG_s
C
I2C_CRC_OUT_BYTE_u
C
I2C_DBG_CTRL_REG_s
C
I2C_DBG_CTRL_u
C
I2C_DESC_REG_s
C
I2C_DESC_u
C
I2C_FIFO_CTRL_REG_s
C
I2C_FIFO_CTRL_u
C
I2C_FIFO_STS_REG_s
C
I2C_FIFO_STS_u
C
I2C_FSM_STATUS_REG_s
C
I2C_FSM_STATUS_u
C
I2C_GLITCH_FILTER_CFG_REG_s
C
I2C_GLITCH_FILTER_CFG_u
C
I2C_INTR_EN_0_REG_s
C
I2C_INTR_EN_0_u
C
I2C_INTR_EN_1_REG_s
C
I2C_INTR_EN_1_u
C
I2C_INTR_EVENT_REG_s
C
I2C_INTR_EVENT_u
C
I2C_INTR_NMI_EN_0_REG_s
C
I2C_INTR_NMI_EN_0_u
C
I2C_INTR_NMI_EN_1_REG_s
C
I2C_INTR_NMI_EN_1_u
C
I2C_INTR_STS_REG_s
C
I2C_INTR_STS_u
C
I2C_INTR_SW_SET_0_REG_s
C
I2C_INTR_SW_SET_0_u
C
I2C_INTR_SW_SET_1_REG_s
C
I2C_INTR_SW_SET_1_u
C
I2C_MASTER_ACK_VAL_REG_s
C
I2C_MASTER_ACK_VAL_u
C
I2C_MASTER_CFG_REG_s
C
I2C_MASTER_CFG_u
C
I2C_MASTER_CLKSTRETCH_CNT_REG_s
C
I2C_MASTER_CLKSTRETCH_CNT_u
C
I2C_MASTER_CTRL_REG_s
C
I2C_MASTER_CTRL_u
C
I2C_MASTER_MON_REG_s
C
I2C_MASTER_MON_u
C
I2C_MASTER_SCL_GEN_REG_s
C
I2C_MASTER_SCL_GEN_u
C
I2C_MASTER_STS_REG_s
C
I2C_MASTER_STS_u
C
I2C_MASTER_TIMING_CONSTRAINT_REG_s
C
I2C_MASTER_TIMING_CONSTRAINT_u
C
I2C_PEC_CTRL_REG_s
C
I2C_PEC_CTRL_u
C
I2C_PEC_STS_REG_s
C
I2C_PEC_STS_u
C
I2C_PWR_EN_REG_s
C
I2C_PWR_EN_u
C
I2C_REGS_s
C
I2C_RST_CTRL_REG_s
C
I2C_RST_CTRL_u
C
I2C_RST_STS_REG_s
C
I2C_RST_STS_u
C
I2C_RX_DMA_EVENT_EN_0_REG_s
C
I2C_RX_DMA_EVENT_EN_0_u
C
I2C_RX_DMA_EVENT_EN_1_REG_s
C
I2C_RX_DMA_EVENT_EN_1_u
C
I2C_RXDATA_REG_s
C
I2C_RXDATA_u
C
I2C_SLAVE_ACK_CFG_REG_s
C
I2C_SLAVE_ACK_CFG_u
C
I2C_SLAVE_ADDR_REG_s
C
I2C_SLAVE_ADDR_u
C
I2C_SLAVE_BYTE_ACK_REG_s
C
I2C_SLAVE_BYTE_ACK_u
C
I2C_SLAVE_CLKSTRETCH_CNT_REG_s
C
I2C_SLAVE_CLKSTRETCH_CNT_u
C
I2C_SLAVE_CTRL_REG_s
C
I2C_SLAVE_CTRL_u
C
I2C_SLAVE_STS_REG_s
C
I2C_SLAVE_STS_u
C
i2c_slv_cfg_t
I2C Configuration in Slave Mode
C
i2c_slv_sts_t
I2C Slave status register struct
C
I2C_SMBUS_TIMEOUT_CNT_REG_s
C
I2C_SMBUS_TIMEOUT_CNT_u
C
I2C_SPARE_CTRL_REG_s
C
I2C_SPARE_CTRL_u
C
I2C_SPARE_STS_REG_s
C
I2C_SPARE_STS_u
C
I2C_TX_DMA_EVENT_EN_0_REG_s
C
I2C_TX_DMA_EVENT_EN_0_u
C
I2C_TX_DMA_EVENT_EN_1_REG_s
C
I2C_TX_DMA_EVENT_EN_1_u
C
I2C_TXDATA_REG_s
C
I2C_TXDATA_u
C
IOMUX_DUMMY_REG_s
C
IOMUX_DUMMY_u
C
IOMUX_PA_REG_s
C
IOMUX_PA_u
C
IOMUX_REGS_s
C
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR)
C
IPSR_Type.b
C
MCU_CTRL_AHB_HCLK_CTRL_REG_s
C
MCU_CTRL_AHB_HCLK_CTRL_u
C
MCU_CTRL_ANA_CLK_EN_REG_s
C
MCU_CTRL_ANA_CLK_EN_u
C
MCU_CTRL_ANA_SPARE_OUT0_REG_s
C
MCU_CTRL_ANA_SPARE_OUT0_u
C
MCU_CTRL_ANA_SPARE_OUT1_REG_s
C
MCU_CTRL_ANA_SPARE_OUT1_u
C
MCU_CTRL_ANA_SPARE_STS_REG_s
C
MCU_CTRL_ANA_SPARE_STS_u
C
MCU_CTRL_AON_CTRL_REG_s
C
MCU_CTRL_AON_CTRL_u
C
MCU_CTRL_APB_PCLK_CTRL_REG_s
C
MCU_CTRL_APB_PCLK_CTRL_u
C
MCU_CTRL_BLOCK_CLK_REQ_REG_s
C
MCU_CTRL_BLOCK_CLK_REQ_u
C
MCU_CTRL_BOOT_CFG_REG_s
C
MCU_CTRL_BOOT_CFG_u
C
MCU_CTRL_BOR_MODE_SEL_REG_s
C
MCU_CTRL_BOR_MODE_SEL_u
C
MCU_CTRL_CLK_4MHZ_CTRL_REG_s
C
MCU_CTRL_CLK_4MHZ_CTRL_u
C
MCU_CTRL_CLK_CTRL_REG_s
C
MCU_CTRL_CLK_CTRL_u
C
MCU_CTRL_CLK_PWR_EN_REG_s
C
MCU_CTRL_CLK_PWR_EN_u
C
MCU_CTRL_DESC_REG_s
C
MCU_CTRL_DESC_u
C
MCU_CTRL_GPAMPCTL_REG_s
C
MCU_CTRL_GPAMPCTL_u
C
MCU_CTRL_GPAMPSTS_REG_s
C
MCU_CTRL_GPAMPSTS_u
C
MCU_CTRL_HF_CLK_CTRL_REG_s
C
MCU_CTRL_HF_CLK_CTRL_u
C
MCU_CTRL_HF_OSC_CLK_CTRL_REG_s
C
MCU_CTRL_HF_OSC_CLK_CTRL_u
C
MCU_CTRL_INTR_EN_REG_s
C
MCU_CTRL_INTR_EN_u
C
MCU_CTRL_INTR_EVENT_REG_s
C
MCU_CTRL_INTR_EVENT_u
C
MCU_CTRL_LF_CLK_CTRL_REG_s
C
MCU_CTRL_LF_CLK_CTRL_u
C
MCU_CTRL_MCU_SW_RST_REG_s
C
MCU_CTRL_MCU_SW_RST_u
C
MCU_CTRL_PLL_CTRL1_REG_s
C
MCU_CTRL_PLL_CTRL1_u
C
MCU_CTRL_PLL_CTRL2_REG_s
C
MCU_CTRL_PLL_CTRL2_u
C
MCU_CTRL_PLL_EN_REG_s
C
MCU_CTRL_PLL_EN_u
C
MCU_CTRL_PMODE_CFG_REG_s
C
MCU_CTRL_PMODE_CFG_u
C
MCU_CTRL_PROCMONCTL_REG_s
C
MCU_CTRL_PROCMONCTL_u
C
MCU_CTRL_PWR_SM_OVRD_CTL_REG_s
C
MCU_CTRL_PWR_SM_OVRD_CTL_u
C
MCU_CTRL_REGS_s
C
MCU_CTRL_RST_CTRL_REG_s
C
MCU_CTRL_RST_CTRL_u
C
MCU_CTRL_RST_STS_REG_s
C
MCU_CTRL_RST_STS_u
C
MCU_CTRL_SPARE_CTRL_REG_s
C
MCU_CTRL_SPARE_CTRL_u
C
MCU_CTRL_SPARE_STS_REG_s
C
MCU_CTRL_SPARE_STS_u
C
MCU_CTRL_XO_CFG_STS_REG_s
C
MCU_CTRL_XO_CFG_STS_u
C
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC)
C
OPAMP_CTRL0_REG_s
C
OPAMP_CTRL0_u
C
OPAMP_DESC_REG_s
C
OPAMP_DESC_u
C
OPAMP_GAIN_CTRL0_REG_s
C
OPAMP_GAIN_CTRL0_u
C
OPAMP_INPUT_CTRL0_REG_s
C
OPAMP_INPUT_CTRL0_u
C
OPAMP_PWR_EN_REG_s
C
OPAMP_PWR_EN_u
C
OPAMP_REGS_s
C
OPAMP_RST_CTRL_REG_s
C
OPAMP_RST_CTRL_u
C
OPAMP_RST_STS_REG_s
C
OPAMP_RST_STS_u
C
OPAMP_SPARE_CTRL_REG_s
C
OPAMP_SPARE_CTRL_u
C
OPAMP_SPARE_STS_REG_s
C
OPAMP_SPARE_STS_u
C
OTP_OTP_CTRL_REG_s
C
OTP_OTP_CTRL_u
C
OTP_OTP_EN_REG_s
C
OTP_OTP_EN_u
C
OTP_OTP_RD_EN_REG_s
C
OTP_OTP_RD_EN_u
C
OTP_OTP_RD_STATUS_REG_s
C
OTP_OTP_RD_STATUS_u
C
OTP_OTP_REG_s
C
OTP_OTP_STATUS_REG_s
C
OTP_OTP_STATUS_u
C
OTP_OTP_u
C
OTP_REGS_s
C
OTP_STS_REG_s
C
OTP_STS_u
C
OTP_TIMER_CTRL_REG_s
C
OTP_TIMER_CTRL_u
C
PL230_ALT_CTRL_BASE_PTR_REG_s
C
PL230_ALT_CTRL_BASE_PTR_u
C
PL230_CHNL_ENABLE_CLR_REG_s
C
PL230_CHNL_ENABLE_CLR_u
C
PL230_CHNL_ENABLE_SET_REG_s
C
PL230_CHNL_ENABLE_SET_u
C
PL230_CHNL_PRI_ALT_CLR_REG_s
C
PL230_CHNL_PRI_ALT_CLR_u
C
PL230_CHNL_PRI_ALT_SET_REG_s
C
PL230_CHNL_PRI_ALT_SET_u
C
PL230_CHNL_PRIORITY_CLR_REG_s
C
PL230_CHNL_PRIORITY_CLR_u
C
PL230_CHNL_PRIORITY_SET_REG_s
C
PL230_CHNL_PRIORITY_SET_u
C
PL230_CHNL_REQ_MASK_CLR_REG_s
C
PL230_CHNL_REQ_MASK_CLR_u
C
PL230_CHNL_REQ_MASK_SET_REG_s
C
PL230_CHNL_REQ_MASK_SET_u
C
PL230_CHNL_SW_REQUEST_REG_s
C
PL230_CHNL_SW_REQUEST_u
C
PL230_CHNL_USEBURST_CLR_REG_s
C
PL230_CHNL_USEBURST_CLR_u
C
PL230_CHNL_USEBURST_SET_REG_s
C
PL230_CHNL_USEBURST_SET_u
C
PL230_CTRL_BASE_PTR_REG_s
C
PL230_CTRL_BASE_PTR_u
C
PL230_DMA_CFG_REG_s
C
PL230_DMA_CFG_u
C
PL230_DMA_STATUS_REG_s
C
PL230_DMA_STATUS_u
C
PL230_DMA_WAITONREQ_STATUS_REG_s
C
PL230_DMA_WAITONREQ_STATUS_u
C
PL230_ERR_CLR_REG_s
C
PL230_ERR_CLR_u
C
PL230_REGS_s
C
RTC_A0_DAY_REG_s
C
RTC_A0_DAY_u
C
RTC_A0_HOUR_REG_s
C
RTC_A0_HOUR_u
C
RTC_A0_MIN_REG_s
C
RTC_A0_MIN_u
C
RTC_A1_DAY_REG_s
C
RTC_A1_DAY_u
C
RTC_A1_HOUR_REG_s
C
RTC_A1_HOUR_u
C
RTC_A1_MIN_REG_s
C
RTC_A1_MIN_u
C
RTC_BUS_CLK_FORCE_REG_s
C
RTC_BUS_CLK_FORCE_u
C
RTC_CLK_CTRL_REG_s
C
RTC_CLK_CTRL_u
C
RTC_DEBUG_CTL_REG_s
C
RTC_DEBUG_CTL_u
C
RTC_DESC_REG_s
C
RTC_DESC_u
C
RTC_DOM_CTL_REG_s
C
RTC_DOM_CTL_u
C
RTC_DOW_CTL_REG_s
C
RTC_DOW_CTL_u
C
RTC_EVENT_EN_REG_s
C
RTC_EVENT_EN_u
C
RTC_HR_CTL_REG_s
C
RTC_HR_CTL_u
C
RTC_INTERVAL_INTR_SEL_REG_s
C
RTC_INTERVAL_INTR_SEL_u
C
RTC_INTR_EN_REG_s
C
RTC_INTR_EN_u
C
RTC_INTR_EVENT_REG_s
C
RTC_INTR_EVENT_u
C
RTC_INTR_NMI_EN_REG_s
C
RTC_INTR_NMI_EN_u
C
RTC_INTR_STS_REG_s
C
RTC_INTR_STS_u
C
RTC_INTR_SW_SET_REG_s
C
RTC_INTR_SW_SET_u
C
RTC_MIN_CTL_REG_s
C
RTC_MIN_CTL_u
C
RTC_MON_CTL_REG_s
C
RTC_MON_CTL_u
C
RTC_PRD_INTR_SEL0_REG_s
C
RTC_PRD_INTR_SEL0_u
C
RTC_PRD_INTR_SEL1_REG_s
C
RTC_PRD_INTR_SEL1_u
C
RTC_PWR_EN_REG_s
C
RTC_PWR_EN_u
C
RTC_REF_DATA_s
C
RTC_REGS_s
C
RTC_RST_CTRL_REG_s
C
RTC_RST_CTRL_u
C
RTC_RST_STS_REG_s
C
RTC_RST_STS_u
C
RTC_RTC_CAL_REG_s
C
RTC_RTC_CAL_u
C
RTC_RTC_CTL_REG_s
C
RTC_RTC_CTL_u
C
RTC_RTC_TEMP_CMP_REG_s
C
RTC_RTC_TEMP_CMP_u
C
RTC_SEC_CTL_REG_s
C
RTC_SEC_CTL_u
C
RTC_YEAR_CTL_REG_s
C
RTC_YEAR_CTL_u
C
SCB_Type
Structure type to access the System Control Block (SCB)
C
spi_cfg_t
SPI Configuation Struct
C
SPI_CLK_CTRL_REG_s
C
SPI_CLK_CTRL_u
C
SPI_CLK_DIV_REG_s
C
SPI_CLK_DIV_u
C
SPI_CLKSEL_REG_s
C
SPI_CLKSEL_u
C
SPI_CMD_DATA_CTRL_REG_s
C
SPI_CMD_DATA_CTRL_u
C
SPI_CS_CTRL_REG_s
C
SPI_CS_CTRL_u
C
SPI_CS_SETUP_HOLD_CNT_REG_s
C
SPI_CS_SETUP_HOLD_CNT_u
C
SPI_DATAFRAME_CTRL_REG_s
C
SPI_DATAFRAME_CTRL_u
C
SPI_DBG_CTRL_REG_s
C
SPI_DBG_CTRL_u
C
SPI_DESC_REG_s
C
SPI_DESC_u
C
SPI_DSPI_CTRL_REG_s
C
SPI_DSPI_CTRL_u
C
SPI_INT_FIFO_LVL_SEL_REG_s
C
SPI_INT_FIFO_LVL_SEL_u
C
SPI_INTR_EN_REG_s
C
SPI_INTR_EN_u
C
SPI_INTR_EVENT_REG_s
C
SPI_INTR_EVENT_u
C
SPI_INTR_NMI_REG_s
C
SPI_INTR_NMI_u
C
SPI_INTR_RX_DMA_EN_REG_s
C
SPI_INTR_RX_DMA_EN_u
C
SPI_INTR_STS_REG_s
C
SPI_INTR_STS_u
C
SPI_INTR_SW_SET_REG_s
C
SPI_INTR_SW_SET_u
C
SPI_INTR_TX_DMA_EN_REG_s
C
SPI_INTR_TX_DMA_EN_u
C
SPI_LOOPBACK_CTRL_REG_s
C
SPI_LOOPBACK_CTRL_u
C
SPI_MODE_CTRL_REG_s
C
SPI_MODE_CTRL_u
C
SPI_MOT_MOD_CNTRL_REG_s
C
SPI_MOT_MOD_CNTRL_u
C
SPI_PARITY_CTRL_REG_s
C
SPI_PARITY_CTRL_u
C
SPI_PWR_EN_REG_s
C
SPI_PWR_EN_u
C
SPI_QSPI_CTRL_REG_s
C
SPI_QSPI_CTRL_u
C
SPI_REGS_s
C
SPI_RST_CTRL_REG_s
C
SPI_RST_CTRL_u
C
SPI_RST_STS_REG_s
C
SPI_RST_STS_u
C
SPI_RX_CTRL_REG_s
C
SPI_RX_CTRL_u
C
SPI_RX_FIFO_REG_s
C
SPI_RX_FIFO_u
C
SPI_SCLK_CTRL_REG_s
C
SPI_SCLK_CTRL_u
C
SPI_SPARE_CTRL_REG_s
C
SPI_SPARE_CTRL_u
C
SPI_SPARE_STS_REG_s
C
SPI_SPARE_STS_u
C
SPI_STS_REG_s
C
SPI_STS_u
C
SPI_TX_CTRL_REG_s
C
SPI_TX_CTRL_u
C
SPI_TX_FIFO_REG_s
C
SPI_TX_FIFO_u
C
SYSCTRL_REGS_s
C
SysTick_Type
Structure type to access the System Timer (SysTick)
C
timer_capture_channel_ctrl_t
C
TIMER_CC0_CAPTURE_CTRL_REG_s
C
TIMER_CC0_CAPTURE_CTRL_u
C
TIMER_CC0_CC_PWM_CFG_REG_s
C
TIMER_CC0_CC_PWM_CFG_u
C
TIMER_CC0_CMN_CTRL_REG_s
C
TIMER_CC0_CMN_CTRL_u
C
TIMER_CC0_COMPARE_CTRL_REG_s
C
TIMER_CC0_COMPARE_CTRL_u
C
TIMER_CC0_OUTPUT_CTL_REG_s
C
TIMER_CC0_OUTPUT_CTL_u
C
TIMER_CC0_SW_FORCE_REG_s
C
TIMER_CC0_SW_FORCE_u
C
TIMER_CC1_CAPTURE_CTRL_REG_s
C
TIMER_CC1_CAPTURE_CTRL_u
C
TIMER_CC1_CC_PWM_CFG_REG_s
C
TIMER_CC1_CC_PWM_CFG_u
C
TIMER_CC1_CMN_CTRL_REG_s
C
TIMER_CC1_CMN_CTRL_u
C
TIMER_CC1_COMPARE_CTRL_REG_s
C
TIMER_CC1_COMPARE_CTRL_u
C
TIMER_CC1_OUTPUT_CTL_REG_s
C
TIMER_CC1_OUTPUT_CTL_u
C
TIMER_CC1_SW_FORCE_REG_s
C
TIMER_CC1_SW_FORCE_u
C
TIMER_CC2_CAPTURE_CTRL_REG_s
C
TIMER_CC2_CAPTURE_CTRL_u
C
TIMER_CC2_CC_PWM_CFG_REG_s
C
TIMER_CC2_CC_PWM_CFG_u
C
TIMER_CC2_CMN_CTRL_REG_s
C
TIMER_CC2_CMN_CTRL_u
C
TIMER_CC2_COMPARE_CTRL_REG_s
C
TIMER_CC2_COMPARE_CTRL_u
C
TIMER_CC2_OUTPUT_CTL_REG_s
C
TIMER_CC2_OUTPUT_CTL_u
C
TIMER_CC2_SW_FORCE_REG_s
C
TIMER_CC2_SW_FORCE_u
C
TIMER_CC3_CAPTURE_CTRL_REG_s
C
TIMER_CC3_CAPTURE_CTRL_u
C
TIMER_CC3_CC_PWM_CFG_REG_s
C
TIMER_CC3_CC_PWM_CFG_u
C
TIMER_CC3_CMN_CTRL_REG_s
C
TIMER_CC3_CMN_CTRL_u
C
TIMER_CC3_COMPARE_CTRL_REG_s
C
TIMER_CC3_COMPARE_CTRL_u
C
TIMER_CC3_OUTPUT_CTL_REG_s
C
TIMER_CC3_OUTPUT_CTL_u
C
TIMER_CC3_SW_FORCE_REG_s
C
TIMER_CC3_SW_FORCE_u
C
TIMER_CC4_CMN_CTRL_REG_s
C
TIMER_CC4_CMN_CTRL_u
C
TIMER_CC4_COMPARE_CTRL_REG_s
C
TIMER_CC4_COMPARE_CTRL_u
C
TIMER_CC5_CMN_CTRL_REG_s
C
TIMER_CC5_CMN_CTRL_u
C
TIMER_CC5_COMPARE_CTRL_REG_s
C
TIMER_CC5_COMPARE_CTRL_u
C
timer_clk_cfg_t
Clock configuration
C
TIMER_CLK_CONFIG_REG_s
C
TIMER_CLK_CONFIG_u
C
TIMER_CLK_CTRL_REG_s
C
TIMER_CLK_CTRL_u
C
timer_ctr_cfg_t
C
TIMER_CTR_CTL_REG_s
C
TIMER_CTR_CTL_u
C
TIMER_CTR_LOAD_VAL_REG_s
C
TIMER_CTR_LOAD_VAL_u
C
TIMER_CTR_PL_VAL_REG_s
C
TIMER_CTR_PL_VAL_u
C
TIMER_CTR_VAL_REG_s
C
TIMER_CTR_VAL_u
C
TIMER_DEADBAND_CFG_REG_s
C
TIMER_DEADBAND_CFG_u
C
TIMER_DEBUG_CTRL_REG_s
C
TIMER_DEBUG_CTRL_u
C
TIMER_DESC_REG_s
C
TIMER_DESC_u
C
TIMER_EVENT_CTRL_REG_s
C
TIMER_EVENT_CTRL_u
C
TIMER_EVENT_EN_0_0_REG_s
C
TIMER_EVENT_EN_0_0_u
C
TIMER_EVENT_EN_0_1_REG_s
C
TIMER_EVENT_EN_0_1_u
C
TIMER_EVENT_EN_1_0_REG_s
C
TIMER_EVENT_EN_1_0_u
C
TIMER_EVENT_EN_1_1_REG_s
C
TIMER_EVENT_EN_1_1_u
C
TIMER_FAULT_IN_CTL_REG_s
C
TIMER_FAULT_IN_CTL_u
C
TIMER_FAULT_SRC_CTL_REG_s
C
TIMER_FAULT_SRC_CTL_u
C
TIMER_INPUT_CC_0_REG_s
C
TIMER_INPUT_CC_0_u
C
TIMER_INPUT_CC_1_REG_s
C
TIMER_INPUT_CC_1_u
C
TIMER_INPUT_CC_2_REG_s
C
TIMER_INPUT_CC_2_u
C
TIMER_INPUT_CC_3_REG_s
C
TIMER_INPUT_CC_3_u
C
timer_input_chan_cfg_t
C
TIMER_INPUT_FILTER_CC_0_REG_s
C
TIMER_INPUT_FILTER_CC_0_u
C
TIMER_INPUT_FILTER_CC_1_REG_s
C
TIMER_INPUT_FILTER_CC_1_u
C
TIMER_INPUT_FILTER_CC_2_REG_s
C
TIMER_INPUT_FILTER_CC_2_u
C
TIMER_INPUT_FILTER_CC_3_REG_s
C
TIMER_INPUT_FILTER_CC_3_u
C
TIMER_INTR_EN_0_REG_s
C
TIMER_INTR_EN_0_u
C
TIMER_INTR_EN_1_REG_s
C
TIMER_INTR_EN_1_u
C
TIMER_INTR_EVENT_REG_s
C
TIMER_INTR_EVENT_u
C
TIMER_INTR_NMI_EN_0_REG_s
C
TIMER_INTR_NMI_EN_0_u
C
TIMER_INTR_NMI_EN_1_REG_s
C
TIMER_INTR_NMI_EN_1_u
C
TIMER_INTR_STS_REG_s
C
TIMER_INTR_STS_u
C
TIMER_INTR_SW_SET_REG_s
C
TIMER_INTR_SW_SET_u
C
timer_output_chan_cfg_t
C
timer_pwm_cfg_t
C
timer_pwm_output_channel_action_cfg_t
C
TIMER_PWR_EN_REG_s
C
TIMER_PWR_EN_u
C
TIMER_QEI_DIR_REG_s
C
TIMER_QEI_DIR_u
C
TIMER_RCTR_LOAD_VAL_REG_s
C
TIMER_RCTR_LOAD_VAL_u
C
TIMER_RCTR_VAL_REG_s
C
TIMER_RCTR_VAL_u
C
TIMER_REGS_s
C
TIMER_RST_CTRL_REG_s
C
TIMER_RST_CTRL_u
C
TIMER_RST_STS_REG_s
C
TIMER_RST_STS_u
C
TIMER_TIMG_NUM_INPUT2_CC0_CAPTURE_CTRL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC0_CAPTURE_CTRL_u
C
TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC0_CC_PWM_CFG_u
C
TIMER_TIMG_NUM_INPUT2_CC0_CMN_CTRL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC0_CMN_CTRL_u
C
TIMER_TIMG_NUM_INPUT2_CC0_COMPARE_CTRL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC0_COMPARE_CTRL_u
C
TIMER_TIMG_NUM_INPUT2_CC0_OUTPUT_CTL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC0_OUTPUT_CTL_u
C
TIMER_TIMG_NUM_INPUT2_CC0_SW_FORCE_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC0_SW_FORCE_u
C
TIMER_TIMG_NUM_INPUT2_CC1_CAPTURE_CTRL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC1_CAPTURE_CTRL_u
C
TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC1_CC_PWM_CFG_u
C
TIMER_TIMG_NUM_INPUT2_CC1_CMN_CTRL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC1_CMN_CTRL_u
C
TIMER_TIMG_NUM_INPUT2_CC1_COMPARE_CTRL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC1_COMPARE_CTRL_u
C
TIMER_TIMG_NUM_INPUT2_CC1_OUTPUT_CTL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC1_OUTPUT_CTL_u
C
TIMER_TIMG_NUM_INPUT2_CC1_SW_FORCE_REG_s
C
TIMER_TIMG_NUM_INPUT2_CC1_SW_FORCE_u
C
TIMER_TIMG_NUM_INPUT2_CLK_CONFIG_REG_s
C
TIMER_TIMG_NUM_INPUT2_CLK_CONFIG_u
C
TIMER_TIMG_NUM_INPUT2_CLK_CTRL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CLK_CTRL_u
C
TIMER_TIMG_NUM_INPUT2_CTR_CTL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CTR_CTL_u
C
TIMER_TIMG_NUM_INPUT2_CTR_LOAD_VAL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CTR_LOAD_VAL_u
C
TIMER_TIMG_NUM_INPUT2_CTR_VAL_REG_s
C
TIMER_TIMG_NUM_INPUT2_CTR_VAL_u
C
TIMER_TIMG_NUM_INPUT2_DEBUG_CTRL_REG_s
C
TIMER_TIMG_NUM_INPUT2_DEBUG_CTRL_u
C
TIMER_TIMG_NUM_INPUT2_DESC_REG_s
C
TIMER_TIMG_NUM_INPUT2_DESC_u
C
TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_REG_s
C
TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_0_u
C
TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_1_REG_s
C
TIMER_TIMG_NUM_INPUT2_EVENT_EN_0_1_u
C
TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_REG_s
C
TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_0_u
C
TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_1_REG_s
C
TIMER_TIMG_NUM_INPUT2_EVENT_EN_1_1_u
C
TIMER_TIMG_NUM_INPUT2_INPUT_CC_0_REG_s
C
TIMER_TIMG_NUM_INPUT2_INPUT_CC_0_u
C
TIMER_TIMG_NUM_INPUT2_INPUT_CC_1_REG_s
C
TIMER_TIMG_NUM_INPUT2_INPUT_CC_1_u
C
TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_0_REG_s
C
TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_0_u
C
TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_1_REG_s
C
TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_1_u
C
TIMER_TIMG_NUM_INPUT2_INTR_EN_0_REG_s
C
TIMER_TIMG_NUM_INPUT2_INTR_EN_0_u
C
TIMER_TIMG_NUM_INPUT2_INTR_EN_1_REG_s
C
TIMER_TIMG_NUM_INPUT2_INTR_EN_1_u
C
TIMER_TIMG_NUM_INPUT2_INTR_EVENT_REG_s
C
TIMER_TIMG_NUM_INPUT2_INTR_EVENT_u
C
TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_REG_s
C
TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_u
C
TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_1_REG_s
C
TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_1_u
C
TIMER_TIMG_NUM_INPUT2_INTR_STS_REG_s
C
TIMER_TIMG_NUM_INPUT2_INTR_STS_u
C
TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_REG_s
C
TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_u
C
TIMER_TIMG_NUM_INPUT2_PWR_EN_REG_s
C
TIMER_TIMG_NUM_INPUT2_PWR_EN_u
C
TIMER_TIMG_NUM_INPUT2_REGS_s
C
TIMER_TIMG_NUM_INPUT2_RST_CTRL_REG_s
C
TIMER_TIMG_NUM_INPUT2_RST_CTRL_u
C
TIMER_TIMG_NUM_INPUT2_RST_STS_REG_s
C
TIMER_TIMG_NUM_INPUT2_RST_STS_u
C
TIMER_TIMG_NUM_INPUT2_TRIG_IN_REG_s
C
TIMER_TIMG_NUM_INPUT2_TRIG_IN_u
C
TIMER_TIMG_NUM_INPUT2_TRIG_OUT_REG_s
C
TIMER_TIMG_NUM_INPUT2_TRIG_OUT_u
C
TIMER_TRIG_IN_REG_s
C
TIMER_TRIG_IN_u
C
TIMER_TRIG_OUT_REG_s
C
TIMER_TRIG_OUT_u
C
UART_ADDR_REG_s
C
UART_ADDR_u
C
UART_ADDRMASK_REG_s
C
UART_ADDRMASK_u
C
UART_BRDDEN_REG_s
C
UART_BRDDEN_u
C
UART_BRDNUM_REG_s
C
UART_BRDNUM_u
C
UART_CFG_REG_s
C
uart_cfg_s
UART Configuration Struct
C
UART_CFG_u
C
UART_CLK_CTRL_REG_s
C
UART_CLK_CTRL_u
C
UART_CLK_DIV_REG_s
C
UART_CLK_DIV_u
C
UART_CLK_SEL_REG_s
C
UART_CLK_SEL_u
C
UART_CLKCFG_REG_s
C
UART_CLKCFG_u
C
UART_CTRL_REG_s
C
UART_CTRL_u
C
UART_DBG_CTRL_REG_s
C
UART_DBG_CTRL_u
C
UART_DESC_REG_s
C
UART_DESC_u
C
UART_DMA_RX_EVENT_EN0_REG_s
C
UART_DMA_RX_EVENT_EN0_u
C
UART_DMA_RX_EVENT_EN1_REG_s
C
UART_DMA_RX_EVENT_EN1_u
C
UART_DMA_TX_EVENT_EN0_REG_s
C
UART_DMA_TX_EVENT_EN0_u
C
UART_DMA_TX_EVENT_EN1_REG_s
C
UART_DMA_TX_EVENT_EN1_u
C
uart_fifo_cfg_s
UART Fifo Configuration Struct
C
UART_FIFOLS_REG_s
C
UART_FIFOLS_u
C
UART_FIFOSTS_REG_s
C
UART_FIFOSTS_u
C
UART_FSM_STS_REG_s
C
UART_FSM_STS_u
C
UART_GFCTL_REG_s
C
UART_GFCTL_u
C
UART_INTR_EN0_REG_s
C
UART_INTR_EN0_u
C
UART_INTR_EN1_REG_s
C
UART_INTR_EN1_u
C
UART_INTR_EVENT_REG_s
C
UART_INTR_EVENT_u
C
UART_INTR_NMI_EN0_REG_s
C
UART_INTR_NMI_EN0_u
C
UART_INTR_NMI_EN1_REG_s
C
UART_INTR_NMI_EN1_u
C
UART_INTR_STS_REG_s
C
UART_INTR_STS_u
C
UART_INTR_SW_SET_REG_s
C
UART_INTR_SW_SET_u
C
UART_PWR_EN_REG_s
C
UART_PWR_EN_u
C
UART_REGS_s
C
UART_RST_CTRL_REG_s
C
UART_RST_CTRL_u
C
UART_RST_STS_REG_s
C
UART_RST_STS_u
C
UART_RXDATA_REG_s
C
UART_RXDATA_u
C
UART_STS_REG_s
C
UART_STS_u
C
UART_TXDATA_REG_s
C
UART_TXDATA_u
C
vref_cfg_s
VREF Configuration Struct
C
VREF_CLK_CTRL_REG_s
C
VREF_CLK_CTRL_u
C
VREF_CTRL_REG_s
C
VREF_CTRL_u
C
VREF_DESC_REG_s
C
VREF_DESC_u
C
VREF_PWR_EN_REG_s
C
VREF_PWR_EN_u
C
VREF_REGS_s
C
VREF_RST_CTRL_REG_s
C
VREF_RST_CTRL_u
C
VREF_RST_STS_REG_s
C
VREF_RST_STS_u
C
VREF_SH_CTRL_REG_s
C
VREF_SH_CTRL_u
C
VREF_SPARE_CTRL_REG_s
C
VREF_SPARE_CTRL_u
C
VREF_SPARE_STS_REG_s
C
VREF_SPARE_STS_u
C
VREF_STS_REG_s
C
VREF_STS_u
C
VULTAN_FLASH_ADDR_REG_s
C
VULTAN_FLASH_ADDR_u
C
VULTAN_FLASH_CTRL_REG_s
C
VULTAN_FLASH_CTRL_u
C
VULTAN_FLASH_DATA0_REG_s
C
VULTAN_FLASH_DATA0_u
C
VULTAN_FLASH_DATA1_REG_s
C
VULTAN_FLASH_DATA1_u
C
VULTAN_FLASH_DATA2_REG_s
C
VULTAN_FLASH_DATA2_u
C
VULTAN_FLASH_DATA3_REG_s
C
VULTAN_FLASH_DATA3_u
C
VULTAN_FLASH_IRQ_ENABLE_CLR_REG_s
C
VULTAN_FLASH_IRQ_ENABLE_CLR_u
C
VULTAN_FLASH_IRQ_ENABLE_SET_REG_s
C
VULTAN_FLASH_IRQ_ENABLE_SET_u
C
VULTAN_FLASH_IRQ_MASKED_STATUS_REG_s
C
VULTAN_FLASH_IRQ_MASKED_STATUS_u
C
VULTAN_FLASH_IRQ_STATUS_CLR_REG_s
C
VULTAN_FLASH_IRQ_STATUS_CLR_u
C
VULTAN_FLASH_IRQ_STATUS_SET_REG_s
C
VULTAN_FLASH_IRQ_STATUS_SET_u
C
VULTAN_FLASH_REGS_s
C
VULTAN_FLASH_STATUS_REG_s
C
VULTAN_FLASH_STATUS_u
C
WATCHDOG_DESC_REG_s
C
WATCHDOG_DESC_u
C
WATCHDOG_EVENT_EN_REG_s
C
WATCHDOG_EVENT_EN_u
C
WATCHDOG_HALT_MODE_REG_s
C
WATCHDOG_HALT_MODE_u
C
WATCHDOG_INTR_EN_REG_s
C
WATCHDOG_INTR_EN_u
C
WATCHDOG_INTR_EVENT_REG_s
C
WATCHDOG_INTR_EVENT_u
C
WATCHDOG_INTR_NMI_EN_REG_s
C
WATCHDOG_INTR_NMI_EN_u
C
WATCHDOG_INTR_STS_REG_s
C
WATCHDOG_INTR_STS_u
C
WATCHDOG_INTR_SW_SET_REG_s
C
WATCHDOG_INTR_SW_SET_u
C
WATCHDOG_PWR_EN_REG_s
C
WATCHDOG_PWR_EN_u
C
WATCHDOG_REGS_s
C
WATCHDOG_RST_CTRL_REG_s
C
WATCHDOG_RST_CTRL_u
C
WATCHDOG_RST_STS_REG_s
C
WATCHDOG_RST_STS_u
C
WATCHDOG_WWDT_CTL0_REG_s
C
WATCHDOG_WWDT_CTL0_u
C
WATCHDOG_WWDT_CTL1_REG_s
C
WATCHDOG_WWDT_CTL1_u
C
WATCHDOG_WWDT_EN_REG_s
C
WATCHDOG_WWDT_EN_u
C
WATCHDOG_WWDT_RESTART_REG_s
C
WATCHDOG_WWDT_RESTART_u
C
WATCHDOG_WWDT_STS_REG_s
C
WATCHDOG_WWDT_STS_u
C
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR)
C
xPSR_Type.b
Generated by
1.14.0
1.14.0 1.14.0