Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

I2C_CLK_CTRL_REG_s : I2C_CLK_CTRL_u
I2C_CRC_OUT_BYTE_REG_s : I2C_CRC_OUT_BYTE_u
I2C_DBG_CTRL_REG_s : I2C_DBG_CTRL_u
I2C_DESC_REG_s : I2C_DESC_u
I2C_FIFO_CTRL_REG_s : I2C_FIFO_CTRL_u
I2C_FIFO_STS_REG_s : I2C_FIFO_STS_u
I2C_FSM_STATUS_REG_s : I2C_FSM_STATUS_u
I2C_GLITCH_FILTER_CFG_REG_s : I2C_GLITCH_FILTER_CFG_u
I2C_INTR_EN_0_REG_s : I2C_INTR_EN_0_u
I2C_INTR_EN_1_REG_s : I2C_INTR_EN_1_u
I2C_INTR_EVENT_REG_s : I2C_INTR_EVENT_u
I2C_INTR_NMI_EN_0_REG_s : I2C_INTR_NMI_EN_0_u
I2C_INTR_NMI_EN_1_REG_s : I2C_INTR_NMI_EN_1_u
I2C_INTR_STS_REG_s : I2C_INTR_STS_u
I2C_INTR_SW_SET_0_REG_s : I2C_INTR_SW_SET_0_u
I2C_INTR_SW_SET_1_REG_s : I2C_INTR_SW_SET_1_u
I2C_MASTER_ACK_VAL_REG_s : I2C_MASTER_ACK_VAL_u
I2C_MASTER_CFG_REG_s : I2C_MASTER_CFG_u
I2C_MASTER_CLKSTRETCH_CNT_REG_s : I2C_MASTER_CLKSTRETCH_CNT_u
I2C_MASTER_CTRL_REG_s : I2C_MASTER_CTRL_u
I2C_MASTER_MON_REG_s : I2C_MASTER_MON_u
I2C_MASTER_SCL_GEN_REG_s : I2C_MASTER_SCL_GEN_u
I2C_MASTER_STS_REG_s : I2C_MASTER_STS_u
I2C_MASTER_TIMING_CONSTRAINT_REG_s : I2C_MASTER_TIMING_CONSTRAINT_u
I2C_PEC_CTRL_REG_s : I2C_PEC_CTRL_u
i2c_pec_en : i2c_slv_cfg_t
I2C_PEC_STS_REG_s : I2C_PEC_STS_u
I2C_PWR_EN_REG_s : I2C_PWR_EN_u
I2C_RST_CTRL_REG_s : I2C_RST_CTRL_u
I2C_RST_STS_REG_s : I2C_RST_STS_u
I2C_RX_DMA_EVENT_EN_0_REG_s : I2C_RX_DMA_EVENT_EN_0_u
I2C_RX_DMA_EVENT_EN_1_REG_s : I2C_RX_DMA_EVENT_EN_1_u
I2C_RXDATA_REG_s : I2C_RXDATA_u
I2C_SLAVE_ACK_CFG_REG_s : I2C_SLAVE_ACK_CFG_u
I2C_SLAVE_ADDR_REG_s : I2C_SLAVE_ADDR_u
I2C_SLAVE_BYTE_ACK_REG_s : I2C_SLAVE_BYTE_ACK_u
I2C_SLAVE_CLKSTRETCH_CNT_REG_s : I2C_SLAVE_CLKSTRETCH_CNT_u
I2C_SLAVE_CTRL_REG_s : I2C_SLAVE_CTRL_u
I2C_SLAVE_STS_REG_s : I2C_SLAVE_STS_u
I2C_SMBUS_TIMEOUT_CNT_REG_s : I2C_SMBUS_TIMEOUT_CNT_u
I2C_SPARE_CTRL_REG_s : I2C_SPARE_CTRL_u
I2C_SPARE_STS_REG_s : I2C_SPARE_STS_u
I2C_TX_DMA_EVENT_EN_0_REG_s : I2C_TX_DMA_EVENT_EN_0_u
I2C_TX_DMA_EVENT_EN_1_REG_s : I2C_TX_DMA_EVENT_EN_1_u
I2C_TXDATA_REG_s : I2C_TXDATA_u
ICER : NVIC_Type
ICPR : NVIC_Type
ICSR : SCB_Type
idle : SPI_INTR_EVENT_REG_s, UART_STS_REG_s
idle_en : SPI_INTR_EN_REG_s
idle_nmi_en : SPI_INTR_NMI_REG_s
idle_rx_dma_en : SPI_INTR_RX_DMA_EN_REG_s
idle_sw_set : SPI_INTR_SW_SET_REG_s
idle_tx_dma_en : SPI_INTR_TX_DMA_EN_REG_s
ignore_rx_cnt : SPI_RX_CTRL_REG_s
in_filter_en : timer_input_chan_cfg_t
in_filter_prd : timer_input_chan_cfg_t
in_inv : timer_input_chan_cfg_t
in_is_big_endian : crc_cfg_s, CRC_CRCCONFIG_REG_s
in_m_en : comp_cfg_s, COMP_INPUT_CTRL0_REG_s
in_m_sel : comp_cfg_s, COMP_INPUT_CTRL0_REG_s, OPAMP_INPUT_CTRL0_REG_s
in_n_sel : OPAMP_INPUT_CTRL0_REG_s
in_p_en : comp_cfg_s, COMP_INPUT_CTRL0_REG_s
in_p_sel : comp_cfg_s, COMP_INPUT_CTRL0_REG_s, OPAMP_INPUT_CTRL0_REG_s
in_sel : timer_input_chan_cfg_t
in_short : comp_cfg_s, COMP_INPUT_CTRL1_REG_s
in_swap : comp_cfg_s, COMP_INPUT_CTRL1_REG_s
input_bit_rev : crc_cfg_s, CRC_CRCCONFIG_REG_s
INPUT_CC_0 : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_INPUT_CC_0_u, TIMER_TIMG_NUM_INPUT2_REGS_s
INPUT_CC_1 : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_INPUT_CC_1_u, TIMER_TIMG_NUM_INPUT2_REGS_s
INPUT_CC_2 : TIMER_REGS_s
INPUT_CC_3 : TIMER_REGS_s
input_clk_rate : adc_samp_timer_cfg_s
INPUT_CTRL0 : COMP_REGS_s, OPAMP_REGS_s
INPUT_CTRL1 : COMP_REGS_s
input_en : IOMUX_PA_REG_s
INPUT_FILTER_CC_0 : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_0_u, TIMER_TIMG_NUM_INPUT2_REGS_s
INPUT_FILTER_CC_1 : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_1_u, TIMER_TIMG_NUM_INPUT2_REGS_s
INPUT_FILTER_CC_2 : TIMER_REGS_s
INPUT_FILTER_CC_3 : TIMER_REGS_s
input_inv_0 : TIMER_INPUT_CC_0_REG_s, TIMER_TIMG_NUM_INPUT2_INPUT_CC_0_REG_s
input_inv_1 : TIMER_INPUT_CC_1_REG_s, TIMER_TIMG_NUM_INPUT2_INPUT_CC_1_REG_s
input_inv_2 : TIMER_INPUT_CC_2_REG_s
input_inv_3 : TIMER_INPUT_CC_3_REG_s
input_sel_0 : TIMER_INPUT_CC_0_REG_s, TIMER_TIMG_NUM_INPUT2_INPUT_CC_0_REG_s
input_sel_1 : TIMER_INPUT_CC_1_REG_s, TIMER_TIMG_NUM_INPUT2_INPUT_CC_1_REG_s
input_sel_2 : TIMER_INPUT_CC_2_REG_s
input_sel_3 : TIMER_INPUT_CC_3_REG_s
input_val : IOMUX_PA_REG_s
INT_FIFO_LVL_SEL : SPI_REGS_s
interval_alarm : RTC_INTR_EVENT_REG_s
interval_alarm_en : RTC_INTR_EN_REG_s
interval_alarm_event_en : RTC_EVENT_EN_REG_s
interval_alarm_nmi_en : RTC_INTR_NMI_EN_REG_s
interval_alarm_sw_set : RTC_INTR_SW_SET_REG_s
INTERVAL_INTR_SEL : RTC_REGS_s
interval_intr_sel : RTC_INTERVAL_INTR_SEL_REG_s
intr0 : GPIO_INTR_EVENT_REG_s
intr0_en : GPIO_INTR_EN0_REG_s
intr0_event_en : GPIO_EVENT_EN0_REG_s
intr0_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr0_sw_set : GPIO_INTR_SW_SET_REG_s
intr1 : GPIO_INTR_EVENT_REG_s
intr10 : GPIO_INTR_EVENT_REG_s
intr10_en : GPIO_INTR_EN0_REG_s
intr10_event_en : GPIO_EVENT_EN0_REG_s
intr10_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr10_sw_set : GPIO_INTR_SW_SET_REG_s
intr11 : GPIO_INTR_EVENT_REG_s
intr11_en : GPIO_INTR_EN0_REG_s
intr11_event_en : GPIO_EVENT_EN0_REG_s
intr11_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr11_sw_set : GPIO_INTR_SW_SET_REG_s
intr12 : GPIO_INTR_EVENT_REG_s
intr12_en : GPIO_INTR_EN0_REG_s
intr12_event_en : GPIO_EVENT_EN0_REG_s
intr12_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr12_sw_set : GPIO_INTR_SW_SET_REG_s
intr13 : GPIO_INTR_EVENT_REG_s
intr13_en : GPIO_INTR_EN0_REG_s
intr13_event_en : GPIO_EVENT_EN0_REG_s
intr13_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr13_sw_set : GPIO_INTR_SW_SET_REG_s
intr14 : GPIO_INTR_EVENT_REG_s
intr14_en : GPIO_INTR_EN0_REG_s
intr14_event_en : GPIO_EVENT_EN0_REG_s
intr14_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr14_sw_set : GPIO_INTR_SW_SET_REG_s
intr15 : GPIO_INTR_EVENT_REG_s
intr15_en : GPIO_INTR_EN0_REG_s
intr15_event_en : GPIO_EVENT_EN0_REG_s
intr15_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr15_sw_set : GPIO_INTR_SW_SET_REG_s
intr16 : GPIO_INTR_EVENT_REG_s
intr16_en : GPIO_INTR_EN1_REG_s
intr16_event_en : GPIO_EVENT_EN1_REG_s
intr16_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr16_sw_set : GPIO_INTR_SW_SET_REG_s
intr17 : GPIO_INTR_EVENT_REG_s
intr17_en : GPIO_INTR_EN1_REG_s
intr17_event_en : GPIO_EVENT_EN1_REG_s
intr17_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr17_sw_set : GPIO_INTR_SW_SET_REG_s
intr18 : GPIO_INTR_EVENT_REG_s
intr18_en : GPIO_INTR_EN1_REG_s
intr18_event_en : GPIO_EVENT_EN1_REG_s
intr18_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr18_sw_set : GPIO_INTR_SW_SET_REG_s
intr19 : GPIO_INTR_EVENT_REG_s
intr19_en : GPIO_INTR_EN1_REG_s
intr19_event_en : GPIO_EVENT_EN1_REG_s
intr19_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr19_sw_set : GPIO_INTR_SW_SET_REG_s
intr1_en : GPIO_INTR_EN0_REG_s
intr1_event_en : GPIO_EVENT_EN0_REG_s
intr1_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr1_sw_set : GPIO_INTR_SW_SET_REG_s
intr2 : GPIO_INTR_EVENT_REG_s
intr20 : GPIO_INTR_EVENT_REG_s
intr20_en : GPIO_INTR_EN1_REG_s
intr20_event_en : GPIO_EVENT_EN1_REG_s
intr20_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr20_sw_set : GPIO_INTR_SW_SET_REG_s
intr21 : GPIO_INTR_EVENT_REG_s
intr21_en : GPIO_INTR_EN1_REG_s
intr21_event_en : GPIO_EVENT_EN1_REG_s
intr21_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr21_sw_set : GPIO_INTR_SW_SET_REG_s
intr22 : GPIO_INTR_EVENT_REG_s
intr22_en : GPIO_INTR_EN1_REG_s
intr22_event_en : GPIO_EVENT_EN1_REG_s
intr22_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr22_sw_set : GPIO_INTR_SW_SET_REG_s
intr23 : GPIO_INTR_EVENT_REG_s
intr23_en : GPIO_INTR_EN1_REG_s
intr23_event_en : GPIO_EVENT_EN1_REG_s
intr23_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr23_sw_set : GPIO_INTR_SW_SET_REG_s
intr24 : GPIO_INTR_EVENT_REG_s
intr24_en : GPIO_INTR_EN1_REG_s
intr24_event_en : GPIO_EVENT_EN1_REG_s
intr24_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr24_sw_set : GPIO_INTR_SW_SET_REG_s
intr25 : GPIO_INTR_EVENT_REG_s
intr25_en : GPIO_INTR_EN1_REG_s
intr25_event_en : GPIO_EVENT_EN1_REG_s
intr25_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr25_sw_set : GPIO_INTR_SW_SET_REG_s
intr26 : GPIO_INTR_EVENT_REG_s
intr26_en : GPIO_INTR_EN1_REG_s
intr26_event_en : GPIO_EVENT_EN1_REG_s
intr26_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr26_sw_set : GPIO_INTR_SW_SET_REG_s
intr27 : GPIO_INTR_EVENT_REG_s
intr27_en : GPIO_INTR_EN1_REG_s
intr27_event_en : GPIO_EVENT_EN1_REG_s
intr27_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr27_sw_set : GPIO_INTR_SW_SET_REG_s
intr28 : GPIO_INTR_EVENT_REG_s
intr28_en : GPIO_INTR_EN1_REG_s
intr28_event_en : GPIO_EVENT_EN1_REG_s
intr28_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr28_sw_set : GPIO_INTR_SW_SET_REG_s
intr29 : GPIO_INTR_EVENT_REG_s
intr29_en : GPIO_INTR_EN1_REG_s
intr29_event_en : GPIO_EVENT_EN1_REG_s
intr29_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr29_sw_set : GPIO_INTR_SW_SET_REG_s
intr2_en : GPIO_INTR_EN0_REG_s
intr2_event_en : GPIO_EVENT_EN0_REG_s
intr2_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr2_sw_set : GPIO_INTR_SW_SET_REG_s
intr3 : GPIO_INTR_EVENT_REG_s
intr30 : GPIO_INTR_EVENT_REG_s
intr30_en : GPIO_INTR_EN1_REG_s
intr30_event_en : GPIO_EVENT_EN1_REG_s
intr30_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr30_sw_set : GPIO_INTR_SW_SET_REG_s
intr31 : GPIO_INTR_EVENT_REG_s
intr31_en : GPIO_INTR_EN1_REG_s
intr31_event_en : GPIO_EVENT_EN1_REG_s
intr31_nmi_en : GPIO_INTR_NMI_EN1_REG_s
intr31_sw_set : GPIO_INTR_SW_SET_REG_s
intr3_en : GPIO_INTR_EN0_REG_s
intr3_event_en : GPIO_EVENT_EN0_REG_s
intr3_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr3_sw_set : GPIO_INTR_SW_SET_REG_s
intr4 : GPIO_INTR_EVENT_REG_s
intr4_en : GPIO_INTR_EN0_REG_s
intr4_event_en : GPIO_EVENT_EN0_REG_s
intr4_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr4_sw_set : GPIO_INTR_SW_SET_REG_s
intr5 : GPIO_INTR_EVENT_REG_s
intr5_en : GPIO_INTR_EN0_REG_s
intr5_event_en : GPIO_EVENT_EN0_REG_s
intr5_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr5_sw_set : GPIO_INTR_SW_SET_REG_s
intr6 : GPIO_INTR_EVENT_REG_s
intr6_en : GPIO_INTR_EN0_REG_s
intr6_event_en : GPIO_EVENT_EN0_REG_s
intr6_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr6_sw_set : GPIO_INTR_SW_SET_REG_s
intr7 : GPIO_INTR_EVENT_REG_s
intr7_en : GPIO_INTR_EN0_REG_s
intr7_event_en : GPIO_EVENT_EN0_REG_s
intr7_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr7_sw_set : GPIO_INTR_SW_SET_REG_s
intr8 : GPIO_INTR_EVENT_REG_s
intr8_en : GPIO_INTR_EN0_REG_s
intr8_event_en : GPIO_EVENT_EN0_REG_s
intr8_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr8_sw_set : GPIO_INTR_SW_SET_REG_s
intr9 : GPIO_INTR_EVENT_REG_s
intr9_en : GPIO_INTR_EN0_REG_s
intr9_event_en : GPIO_EVENT_EN0_REG_s
intr9_nmi_en : GPIO_INTR_NMI_EN0_REG_s
intr9_sw_set : GPIO_INTR_SW_SET_REG_s
intr_edge_sel : comp_cfg_s, COMP_CTRL0_REG_s
INTR_EN : COMP_REGS_s, DAC_REGS_s, MCU_CTRL_REGS_s, RTC_REGS_s, SPI_REGS_s, WATCHDOG_REGS_s
INTR_EN0 : GPIO_REGS_s, UART_REGS_s
INTR_EN1 : GPIO_REGS_s, UART_REGS_s
INTR_EN_0 : ADC_REGS_s, DMA_REGS_s, I2C_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_0_u, TIMER_TIMG_NUM_INPUT2_REGS_s
INTR_EN_1 : ADC_REGS_s, DMA_REGS_s, I2C_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_INTR_EN_1_u, TIMER_TIMG_NUM_INPUT2_REGS_s
intr_en_during_debug : RTC_DEBUG_CTL_REG_s
INTR_EVENT : ADC_REGS_s, COMP_REGS_s, DAC_REGS_s, DMA_REGS_s, GPIO_REGS_s, I2C_REGS_s, MCU_CTRL_REGS_s, RTC_REGS_s, SPI_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_INTR_EVENT_u, TIMER_TIMG_NUM_INPUT2_REGS_s, UART_REGS_s, WATCHDOG_REGS_s
intr_first : ADC_INTR_STS_REG_s, COMP_INTR_STS_REG_s, DAC_INTR_STS_REG_s, DMA_INTR_STS_REG_s, GPIO_INTR_STS_REG_s, I2C_INTR_STS_REG_s, RTC_INTR_STS_REG_s, SPI_INTR_STS_REG_s, TIMER_INTR_STS_REG_s, TIMER_TIMG_NUM_INPUT2_INTR_STS_REG_s, UART_INTR_STS_REG_s, WATCHDOG_INTR_STS_REG_s
INTR_NMI : SPI_REGS_s
INTR_NMI_EN : COMP_REGS_s, DAC_REGS_s, RTC_REGS_s, WATCHDOG_REGS_s
INTR_NMI_EN0 : GPIO_REGS_s, UART_REGS_s
INTR_NMI_EN1 : GPIO_REGS_s, UART_REGS_s
INTR_NMI_EN_0 : ADC_REGS_s, DMA_REGS_s, I2C_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_0_u, TIMER_TIMG_NUM_INPUT2_REGS_s
INTR_NMI_EN_1 : ADC_REGS_s, DMA_REGS_s, I2C_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_INTR_NMI_EN_1_u, TIMER_TIMG_NUM_INPUT2_REGS_s
INTR_POL_0 : GPIO_REGS_s
intr_pol_0 : GPIO_INTR_POL_0_REG_s
INTR_POL_1 : GPIO_REGS_s
intr_pol_1 : GPIO_INTR_POL_0_REG_s
intr_pol_10 : GPIO_INTR_POL_0_REG_s
intr_pol_11 : GPIO_INTR_POL_0_REG_s
intr_pol_12 : GPIO_INTR_POL_0_REG_s
intr_pol_13 : GPIO_INTR_POL_0_REG_s
intr_pol_14 : GPIO_INTR_POL_0_REG_s
intr_pol_15 : GPIO_INTR_POL_0_REG_s
intr_pol_16 : GPIO_INTR_POL_1_REG_s
intr_pol_17 : GPIO_INTR_POL_1_REG_s
intr_pol_18 : GPIO_INTR_POL_1_REG_s
intr_pol_19 : GPIO_INTR_POL_1_REG_s
intr_pol_2 : GPIO_INTR_POL_0_REG_s
intr_pol_20 : GPIO_INTR_POL_1_REG_s
intr_pol_21 : GPIO_INTR_POL_1_REG_s
intr_pol_22 : GPIO_INTR_POL_1_REG_s
intr_pol_23 : GPIO_INTR_POL_1_REG_s
intr_pol_24 : GPIO_INTR_POL_1_REG_s
intr_pol_25 : GPIO_INTR_POL_1_REG_s
intr_pol_26 : GPIO_INTR_POL_1_REG_s
intr_pol_27 : GPIO_INTR_POL_1_REG_s
intr_pol_28 : GPIO_INTR_POL_1_REG_s
intr_pol_29 : GPIO_INTR_POL_1_REG_s
intr_pol_3 : GPIO_INTR_POL_0_REG_s
intr_pol_30 : GPIO_INTR_POL_1_REG_s
intr_pol_31 : GPIO_INTR_POL_1_REG_s
intr_pol_4 : GPIO_INTR_POL_0_REG_s
intr_pol_5 : GPIO_INTR_POL_0_REG_s
intr_pol_6 : GPIO_INTR_POL_0_REG_s
intr_pol_7 : GPIO_INTR_POL_0_REG_s
intr_pol_8 : GPIO_INTR_POL_0_REG_s
intr_pol_9 : GPIO_INTR_POL_0_REG_s
INTR_RX_DMA_EN : SPI_REGS_s
INTR_STS : ADC_REGS_s, COMP_REGS_s, DAC_REGS_s, DMA_REGS_s, GPIO_REGS_s, I2C_REGS_s, RTC_REGS_s, SPI_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_INTR_STS_u, TIMER_TIMG_NUM_INPUT2_REGS_s, UART_REGS_s, WATCHDOG_REGS_s
INTR_SW : ADC_REGS_s
INTR_SW_SET : COMP_REGS_s, DAC_REGS_s, DMA_REGS_s, GPIO_REGS_s, RTC_REGS_s, SPI_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_INTR_SW_SET_u, TIMER_TIMG_NUM_INPUT2_REGS_s, UART_REGS_s, WATCHDOG_REGS_s
INTR_SW_SET_0 : I2C_REGS_s
INTR_SW_SET_1 : I2C_REGS_s
INTR_TX_DMA_EN : SPI_REGS_s
IOMUX_DUMMY_REG_s : IOMUX_DUMMY_u
IOMUX_PA_REG_s : IOMUX_PA_u
IP : NVIC_Type
IRQ_ENABLE_CLR : VULTAN_FLASH_REGS_s
IRQ_ENABLE_SET : VULTAN_FLASH_REGS_s
IRQ_MASKED_STATUS : VULTAN_FLASH_REGS_s
IRQ_STATUS_CLR : VULTAN_FLASH_REGS_s
IRQ_STATUS_SET : VULTAN_FLASH_REGS_s
is_capture_0 : TIMER_CC0_CMN_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC0_CMN_CTRL_REG_s
is_capture_1 : TIMER_CC1_CMN_CTRL_REG_s, TIMER_TIMG_NUM_INPUT2_CC1_CMN_CTRL_REG_s
is_capture_2 : TIMER_CC2_CMN_CTRL_REG_s
is_capture_3 : TIMER_CC3_CMN_CTRL_REG_s
is_consecutive_prd_0 : TIMER_INPUT_FILTER_CC_0_REG_s, TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_0_REG_s
is_consecutive_prd_1 : TIMER_INPUT_FILTER_CC_1_REG_s, TIMER_TIMG_NUM_INPUT2_INPUT_FILTER_CC_1_REG_s
is_consecutive_prd_2 : TIMER_INPUT_FILTER_CC_2_REG_s
is_consecutive_prd_3 : TIMER_INPUT_FILTER_CC_3_REG_s
is_timer_mode : WATCHDOG_WWDT_CTL0_REG_s
isavb : FLASH_CTRL_REG_s
ISER : NVIC_Type
ISPR : NVIC_Type
ISR : IPSR_Type.b, xPSR_Type.b
IT : xPSR_Type.b