Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

DAC_CAL_CTRL_REG_s : DAC_CAL_CTRL_u
DAC_CAL_STS_REG_s : DAC_CAL_STS_u
DAC_CLK_CTRL_REG_s : DAC_CLK_CTRL_u
dac_code : DAC_DATA_REG_s
dac_code0 : COMP_REF_CTRL1_REG_s
dac_code1 : COMP_REF_CTRL1_REG_s
dac_code_sel : COMP_REF_CTRL1_REG_s
DAC_CTRL0_REG_s : DAC_CTRL0_u
DAC_CTRL1_REG_s : DAC_CTRL1_u
DAC_CTRL2_REG_s : DAC_CTRL2_u
DAC_CTRL3_REG_s : DAC_CTRL3_u
DAC_DATA_REG_s : DAC_DATA_u
DAC_DESC_REG_s : DAC_DESC_u
DAC_EVENT_CTRL_REG_s : DAC_EVENT_CTRL_u
DAC_EVENT_EN_REG_s : DAC_EVENT_EN_u
DAC_INTR_EN_REG_s : DAC_INTR_EN_u
DAC_INTR_EVENT_REG_s : DAC_INTR_EVENT_u
DAC_INTR_NMI_EN_REG_s : DAC_INTR_NMI_EN_u
DAC_INTR_STS_REG_s : DAC_INTR_STS_u
DAC_INTR_SW_SET_REG_s : DAC_INTR_SW_SET_u
dac_mode : COMP_REF_CTRL1_REG_s
DAC_PWR_EN_REG_s : DAC_PWR_EN_u
dac_rdy : DAC_INTR_EVENT_REG_s
dac_rdy_en : DAC_INTR_EN_REG_s
dac_rdy_event_en : DAC_EVENT_EN_REG_s
dac_rdy_nmi_en : DAC_INTR_NMI_EN_REG_s
dac_rdy_sw_set : DAC_INTR_SW_SET_REG_s
DAC_RST_CTRL_REG_s : DAC_RST_CTRL_u
DAC_RST_STS_REG_s : DAC_RST_STS_u
DAC_SPARE_CTRL_REG_s : DAC_SPARE_CTRL_u
DAC_SPARE_STS_REG_s : DAC_SPARE_STS_u
DAP_ACCESS : BOOTLOADER_BCR_CFG0_REG_s
DATA : DAC_REGS_s
data : CRC_CRCINPUT_REG_s
DATA0 : VULTAN_FLASH_REGS_s
data0 : VULTAN_FLASH_DATA0_REG_s
DATA1 : VULTAN_FLASH_REGS_s
data1 : VULTAN_FLASH_DATA1_REG_s
DATA2 : VULTAN_FLASH_REGS_s
data2 : VULTAN_FLASH_DATA2_REG_s
DATA3 : VULTAN_FLASH_REGS_s
data3 : VULTAN_FLASH_DATA3_REG_s
data_channel : adc_chnl_cfg_s
data_fmt : dac_cfg_s, DAC_CTRL0_REG_s
data_out_disable : SPI_DATAFRAME_CTRL_REG_s
data_size_sel : spi_cfg_t, SPI_DATAFRAME_CTRL_REG_s
DATAFRAME_CTRL : SPI_REGS_s
db_fall_delay : TIMER_DEADBAND_CFG_REG_s
db_mode : TIMER_DEADBAND_CFG_REG_s
db_rise_delay : TIMER_DEADBAND_CFG_REG_s
DBG_CTRL : ADC_REGS_s, DMA_REGS_s, I2C_REGS_s, SPI_REGS_s, UART_REGS_s
DEADBAND_CFG : TIMER_REGS_s
DEBUG_CTL : RTC_REGS_s
DEBUG_CTRL : TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_DEBUG_CTRL_u, TIMER_TIMG_NUM_INPUT2_REGS_s
den_n : UART_BRDDEN_REG_s
DESC : ADC_REGS_s, COMP_REGS_s, DAC_REGS_s, DMA_REGS_s, EVENT_FABRIC_REGS_s, FLASH_REGS_s, GPIO_REGS_s, I2C_REGS_s, MCU_CTRL_REGS_s, OPAMP_REGS_s, RTC_REGS_s, SPI_REGS_s, TIMER_REGS_s, TIMER_TIMG_NUM_INPUT2_DESC_u, TIMER_TIMG_NUM_INPUT2_REGS_s, UART_REGS_s, VREF_REGS_s, WATCHDOG_REGS_s
DIN : GPIO_REGS_s
din : GPIO_DIN_REG_s
din_0 : GPIO_DIN_3_0_REG_s
din_1 : GPIO_DIN_3_0_REG_s
din_10 : GPIO_DIN_11_8_REG_s
din_11 : GPIO_DIN_11_8_REG_s
DIN_11_8 : GPIO_REGS_s
din_12 : GPIO_DIN_15_12_REG_s
din_13 : GPIO_DIN_15_12_REG_s
din_14 : GPIO_DIN_15_12_REG_s
din_15 : GPIO_DIN_15_12_REG_s
DIN_15_12 : GPIO_REGS_s
din_16 : GPIO_DIN_19_16_REG_s
din_17 : GPIO_DIN_19_16_REG_s
din_18 : GPIO_DIN_19_16_REG_s
din_19 : GPIO_DIN_19_16_REG_s
DIN_19_16 : GPIO_REGS_s
din_2 : GPIO_DIN_3_0_REG_s
din_20 : GPIO_DIN_23_20_REG_s
din_21 : GPIO_DIN_23_20_REG_s
din_22 : GPIO_DIN_23_20_REG_s
din_23 : GPIO_DIN_23_20_REG_s
DIN_23_20 : GPIO_REGS_s
din_24 : GPIO_DIN_27_24_REG_s
din_25 : GPIO_DIN_27_24_REG_s
din_26 : GPIO_DIN_27_24_REG_s
din_27 : GPIO_DIN_27_24_REG_s
DIN_27_24 : GPIO_REGS_s
din_28 : GPIO_DIN_31_28_REG_s
din_29 : GPIO_DIN_31_28_REG_s
din_3 : GPIO_DIN_3_0_REG_s
din_30 : GPIO_DIN_31_28_REG_s
din_31 : GPIO_DIN_31_28_REG_s
DIN_31_28 : GPIO_REGS_s
DIN_3_0 : GPIO_REGS_s
din_4 : GPIO_DIN_7_4_REG_s
din_5 : GPIO_DIN_7_4_REG_s
din_6 : GPIO_DIN_7_4_REG_s
din_7 : GPIO_DIN_7_4_REG_s
DIN_7_4 : GPIO_REGS_s
din_8 : GPIO_DIN_11_8_REG_s
din_9 : GPIO_DIN_11_8_REG_s
div_ratio : SPI_CLK_DIV_REG_s
dly_sample_on_rx : SPI_RX_CTRL_REG_s
DMA_ARBITRATION_MASK_REG_s : DMA_ARBITRATION_MASK_u
DMA_ARBITRATION_REG_s : DMA_ARBITRATION_u
DMA_CFG : PL230_REGS_s
DMA_CFG_0_REG_s : DMA_CFG_0_u
DMA_CFG_1_REG_s : DMA_CFG_1_u
DMA_CFG_2_REG_s : DMA_CFG_2_u
DMA_CLK_CTRL_REG_s : DMA_CLK_CTRL_u
DMA_DBG_CTRL_REG_s : DMA_DBG_CTRL_u
DMA_DESC_REG_s : DMA_DESC_u
dma_done : ADC_INTR_EVENT_REG_s, DAC_INTR_EVENT_REG_s
dma_done_0 : DMA_INTR_EVENT_REG_s
dma_done_1 : DMA_INTR_EVENT_REG_s
dma_done_10 : DMA_INTR_EVENT_REG_s
dma_done_11 : DMA_INTR_EVENT_REG_s
dma_done_12 : DMA_INTR_EVENT_REG_s
dma_done_13 : DMA_INTR_EVENT_REG_s
dma_done_14 : DMA_INTR_EVENT_REG_s
dma_done_15 : DMA_INTR_EVENT_REG_s
dma_done_2 : DMA_INTR_EVENT_REG_s
dma_done_3 : DMA_INTR_EVENT_REG_s
dma_done_4 : DMA_INTR_EVENT_REG_s
dma_done_5 : DMA_INTR_EVENT_REG_s
dma_done_6 : DMA_INTR_EVENT_REG_s
dma_done_7 : DMA_INTR_EVENT_REG_s
dma_done_8 : DMA_INTR_EVENT_REG_s
dma_done_9 : DMA_INTR_EVENT_REG_s
dma_done_dma_en : ADC_DMA_EVENT_EN_0_REG_s
dma_done_en : ADC_INTR_EN_0_REG_s, DAC_INTR_EN_REG_s
dma_done_en_0 : DMA_INTR_EN_0_REG_s
dma_done_en_1 : DMA_INTR_EN_0_REG_s
dma_done_en_10 : DMA_INTR_EN_0_REG_s
dma_done_en_11 : DMA_INTR_EN_0_REG_s
dma_done_en_12 : DMA_INTR_EN_0_REG_s
dma_done_en_13 : DMA_INTR_EN_0_REG_s
dma_done_en_14 : DMA_INTR_EN_0_REG_s
dma_done_en_15 : DMA_INTR_EN_0_REG_s
dma_done_en_2 : DMA_INTR_EN_0_REG_s
dma_done_en_3 : DMA_INTR_EN_0_REG_s
dma_done_en_4 : DMA_INTR_EN_0_REG_s
dma_done_en_5 : DMA_INTR_EN_0_REG_s
dma_done_en_6 : DMA_INTR_EN_0_REG_s
dma_done_en_7 : DMA_INTR_EN_0_REG_s
dma_done_en_8 : DMA_INTR_EN_0_REG_s
dma_done_en_9 : DMA_INTR_EN_0_REG_s
dma_done_event_en : ADC_EVENT_EN_0_REG_s, DAC_EVENT_EN_REG_s
dma_done_event_en_0 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_1 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_10 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_11 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_12 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_13 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_14 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_15 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_2 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_3 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_4 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_5 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_6 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_7 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_8 : DMA_EVENT_EN_0_REG_s
dma_done_event_en_9 : DMA_EVENT_EN_0_REG_s
dma_done_nmi_en : ADC_INTR_NMI_EN_0_REG_s, DAC_INTR_NMI_EN_REG_s
dma_done_nmi_en_0 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_1 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_10 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_11 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_12 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_13 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_14 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_15 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_2 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_3 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_4 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_5 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_6 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_7 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_8 : DMA_INTR_NMI_EN_0_REG_s
dma_done_nmi_en_9 : DMA_INTR_NMI_EN_0_REG_s
dma_done_rx : I2C_INTR_EVENT_REG_s
dma_done_rx_en : I2C_INTR_EN_1_REG_s
dma_done_rx_intr : UART_INTR_EVENT_REG_s
dma_done_rx_intr_en : UART_INTR_EN1_REG_s
dma_done_rx_intr_nmi_en : UART_INTR_NMI_EN1_REG_s
dma_done_rx_intr_sw_set : UART_INTR_SW_SET_REG_s
dma_done_rx_nmi_en : I2C_INTR_NMI_EN_1_REG_s
dma_done_rx_sw_set : I2C_INTR_SW_SET_1_REG_s
dma_done_sw_set : ADC_INTR_SW_REG_s, DAC_INTR_SW_SET_REG_s
dma_done_sw_set_0 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_1 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_10 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_11 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_12 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_13 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_14 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_15 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_2 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_3 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_4 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_5 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_6 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_7 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_8 : DMA_INTR_SW_SET_REG_s
dma_done_sw_set_9 : DMA_INTR_SW_SET_REG_s
dma_done_tx : I2C_INTR_EVENT_REG_s
dma_done_tx_en : I2C_INTR_EN_1_REG_s
dma_done_tx_intr : UART_INTR_EVENT_REG_s
dma_done_tx_intr_en : UART_INTR_EN1_REG_s
dma_done_tx_intr_nmi_en : UART_INTR_NMI_EN1_REG_s
dma_done_tx_intr_sw_set : UART_INTR_SW_SET_REG_s
dma_done_tx_nmi_en : I2C_INTR_NMI_EN_1_REG_s
dma_done_tx_sw_set : I2C_INTR_SW_SET_1_REG_s
DMA_EARLY_IRQ_0_REG_s : DMA_EARLY_IRQ_0_u
DMA_EARLY_IRQ_10_REG_s : DMA_EARLY_IRQ_10_u
DMA_EARLY_IRQ_11_REG_s : DMA_EARLY_IRQ_11_u
DMA_EARLY_IRQ_12_REG_s : DMA_EARLY_IRQ_12_u
DMA_EARLY_IRQ_13_REG_s : DMA_EARLY_IRQ_13_u
DMA_EARLY_IRQ_14_REG_s : DMA_EARLY_IRQ_14_u
DMA_EARLY_IRQ_15_REG_s : DMA_EARLY_IRQ_15_u
DMA_EARLY_IRQ_1_REG_s : DMA_EARLY_IRQ_1_u
DMA_EARLY_IRQ_2_REG_s : DMA_EARLY_IRQ_2_u
DMA_EARLY_IRQ_3_REG_s : DMA_EARLY_IRQ_3_u
DMA_EARLY_IRQ_4_REG_s : DMA_EARLY_IRQ_4_u
DMA_EARLY_IRQ_5_REG_s : DMA_EARLY_IRQ_5_u
DMA_EARLY_IRQ_6_REG_s : DMA_EARLY_IRQ_6_u
DMA_EARLY_IRQ_7_REG_s : DMA_EARLY_IRQ_7_u
DMA_EARLY_IRQ_8_REG_s : DMA_EARLY_IRQ_8_u
DMA_EARLY_IRQ_9_REG_s : DMA_EARLY_IRQ_9_u
DMA_EARLY_IRQ_CFG_REG_s : DMA_EARLY_IRQ_CFG_u
dma_en : adc_dma_cfg_s, ADC_DMA_REG_REG_s, adc_multi_ch_conv_cfg_s, adc_single_ch_conv_cfg_s
DMA_EVENT_EN_0 : ADC_REGS_s
DMA_EVENT_EN_0_REG_s : DMA_EVENT_EN_0_u
DMA_EVENT_EN_1 : ADC_REGS_s
DMA_EVENT_EN_1_REG_s : DMA_EVENT_EN_1_u
DMA_FILL_MODE_CFG_REG_s : DMA_FILL_MODE_CFG_u
DMA_FILL_MODE_REG_s : DMA_FILL_MODE_u
DMA_INTR_EN_0_REG_s : DMA_INTR_EN_0_u
DMA_INTR_EN_1_REG_s : DMA_INTR_EN_1_u
DMA_INTR_EVENT_REG_s : DMA_INTR_EVENT_u
DMA_INTR_NMI_EN_0_REG_s : DMA_INTR_NMI_EN_0_u
DMA_INTR_NMI_EN_1_REG_s : DMA_INTR_NMI_EN_1_u
DMA_INTR_STS_REG_s : DMA_INTR_STS_u
DMA_INTR_SW_SET_REG_s : DMA_INTR_SW_SET_u
DMA_PUB : EVENT_FABRIC_REGS_s
dma_pub_event_id : EVENT_FABRIC_DMA_PUB_REG_s
DMA_PWR_EN_REG_s : DMA_PWR_EN_u
DMA_REG : ADC_REGS_s
DMA_REPEATED_TRANSFER_ALTERNATE_SEL_REG_s : DMA_REPEATED_TRANSFER_ALTERNATE_SEL_u
DMA_REPEATED_TRANSFER_CHNL_0_REG_s : DMA_REPEATED_TRANSFER_CHNL_0_u
DMA_REPEATED_TRANSFER_CHNL_10_REG_s : DMA_REPEATED_TRANSFER_CHNL_10_u
DMA_REPEATED_TRANSFER_CHNL_11_REG_s : DMA_REPEATED_TRANSFER_CHNL_11_u
DMA_REPEATED_TRANSFER_CHNL_12_REG_s : DMA_REPEATED_TRANSFER_CHNL_12_u
DMA_REPEATED_TRANSFER_CHNL_13_REG_s : DMA_REPEATED_TRANSFER_CHNL_13_u
DMA_REPEATED_TRANSFER_CHNL_14_REG_s : DMA_REPEATED_TRANSFER_CHNL_14_u
DMA_REPEATED_TRANSFER_CHNL_15_REG_s : DMA_REPEATED_TRANSFER_CHNL_15_u
DMA_REPEATED_TRANSFER_CHNL_1_REG_s : DMA_REPEATED_TRANSFER_CHNL_1_u
DMA_REPEATED_TRANSFER_CHNL_2_REG_s : DMA_REPEATED_TRANSFER_CHNL_2_u
DMA_REPEATED_TRANSFER_CHNL_3_REG_s : DMA_REPEATED_TRANSFER_CHNL_3_u
DMA_REPEATED_TRANSFER_CHNL_4_REG_s : DMA_REPEATED_TRANSFER_CHNL_4_u
DMA_REPEATED_TRANSFER_CHNL_5_REG_s : DMA_REPEATED_TRANSFER_CHNL_5_u
DMA_REPEATED_TRANSFER_CHNL_6_REG_s : DMA_REPEATED_TRANSFER_CHNL_6_u
DMA_REPEATED_TRANSFER_CHNL_7_REG_s : DMA_REPEATED_TRANSFER_CHNL_7_u
DMA_REPEATED_TRANSFER_CHNL_8_REG_s : DMA_REPEATED_TRANSFER_CHNL_8_u
DMA_REPEATED_TRANSFER_CHNL_9_REG_s : DMA_REPEATED_TRANSFER_CHNL_9_u
DMA_REPEATED_TRANSFER_EN_REG_s : DMA_REPEATED_TRANSFER_EN_u
dma_rr_en : DMA_ARBITRATION_REG_s
dma_rr_mask : DMA_ARBITRATION_MASK_REG_s
DMA_RST_CTRL_REG_s : DMA_RST_CTRL_u
DMA_RST_STS_REG_s : DMA_RST_STS_u
dma_rx_addr_match_en : UART_DMA_RX_EVENT_EN1_REG_s
dma_rx_baud_err_en : UART_DMA_RX_EVENT_EN1_REG_s
dma_rx_cts_int_en : UART_DMA_RX_EVENT_EN1_REG_s
dma_rx_dma_done_rx_intr_en : UART_DMA_RX_EVENT_EN1_REG_s
dma_rx_dma_done_tx_intr_en : UART_DMA_RX_EVENT_EN1_REG_s
dma_rx_eot_en : UART_DMA_RX_EVENT_EN1_REG_s
DMA_RX_EVENT_EN0 : UART_REGS_s
DMA_RX_EVENT_EN1 : UART_REGS_s
dma_rx_frame_err_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_maj_vote_err_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_overflow_err_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_parity_err_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_rcv_negedge_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_rcv_posedge_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_rcv_timeout_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_rx_fifo_almost_empty_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_rx_fifo_almost_full_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_rx_fifo_empty_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_rx_fifo_full_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_rx_int_en : UART_DMA_RX_EVENT_EN1_REG_s
dma_rx_tx_fifo_almost_empty_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_tx_fifo_almost_full_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_tx_fifo_empty_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_tx_fifo_full_en : UART_DMA_RX_EVENT_EN0_REG_s
dma_rx_tx_int_en : UART_DMA_RX_EVENT_EN1_REG_s
dma_rx_underflow_err_en : UART_DMA_RX_EVENT_EN0_REG_s
DMA_STATUS : PL230_REGS_s
DMA_STRIDE_MODE_CFG_0_REG_s : DMA_STRIDE_MODE_CFG_0_u
DMA_STRIDE_MODE_CFG_1_REG_s : DMA_STRIDE_MODE_CFG_1_u
DMA_STRIDE_MODE_CFG_2_REG_s : DMA_STRIDE_MODE_CFG_2_u
DMA_STRIDE_MODE_REG_s : DMA_STRIDE_MODE_u
DMA_TRANSFER_CNT : ADC_REGS_s
dma_transfer_cnt : adc_dma_cfg_s, ADC_DMA_TRANSFER_CNT_REG_s, adc_multi_ch_conv_cfg_s, adc_single_ch_conv_cfg_s
dma_trig_en : DAC_CTRL2_REG_s, dac_dma_cfg_s
dma_tx_addr_match_en : UART_DMA_TX_EVENT_EN1_REG_s
dma_tx_baud_err_en : UART_DMA_TX_EVENT_EN1_REG_s
dma_tx_cts_int_en : UART_DMA_TX_EVENT_EN1_REG_s
dma_tx_dma_done_rx_intr_en : UART_DMA_TX_EVENT_EN1_REG_s
dma_tx_dma_done_tx_intr_en : UART_DMA_TX_EVENT_EN1_REG_s
dma_tx_eot_en : UART_DMA_TX_EVENT_EN1_REG_s
DMA_TX_EVENT_EN0 : UART_REGS_s
DMA_TX_EVENT_EN1 : UART_REGS_s
dma_tx_frame_err_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_maj_vote_err_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_overflow_err_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_parity_err_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_rcv_negedge_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_rcv_posedge_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_rcv_timeout_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_rx_fifo_almost_empty_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_rx_fifo_almost_full_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_rx_fifo_empty_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_rx_fifo_full_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_rx_int_en : UART_DMA_TX_EVENT_EN1_REG_s
dma_tx_tx_fifo_almost_empty_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_tx_fifo_almost_full_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_tx_fifo_empty_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_tx_fifo_full_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_tx_tx_int_en : UART_DMA_TX_EVENT_EN1_REG_s
dma_tx_underflow_err_en : UART_DMA_TX_EVENT_EN0_REG_s
dma_waitonreg_status : PL230_DMA_WAITONREQ_STATUS_REG_s
DMA_WAITONREQ_REG_s : DMA_WAITONREQ_u
DMA_WAITONREQ_STATUS : PL230_REGS_s
DMA_WR_MASK : GPIO_REGS_s
dma_wr_mask : GPIO_DMA_WR_MASK_REG_s
dom_bin : RTC_DOM_CTL_REG_s
DOM_CTL : RTC_REGS_s
dom_lsb_bcd : RTC_DOM_CTL_REG_s
dom_msb_bcd : RTC_DOM_CTL_REG_s
dom_rtc_rdy : RTC_DOM_CTL_REG_s
DOUT : GPIO_REGS_s
dout : GPIO_DOUT_REG_s
dout_0 : GPIO_DOUT_3_0_REG_s
dout_1 : GPIO_DOUT_3_0_REG_s
dout_10 : GPIO_DOUT_11_8_REG_s
dout_11 : GPIO_DOUT_11_8_REG_s
DOUT_11_8 : GPIO_REGS_s
dout_12 : GPIO_DOUT_15_12_REG_s
dout_13 : GPIO_DOUT_15_12_REG_s
dout_14 : GPIO_DOUT_15_12_REG_s
dout_15 : GPIO_DOUT_15_12_REG_s
DOUT_15_12 : GPIO_REGS_s
dout_16 : GPIO_DOUT_19_16_REG_s
dout_17 : GPIO_DOUT_19_16_REG_s
dout_18 : GPIO_DOUT_19_16_REG_s
dout_19 : GPIO_DOUT_19_16_REG_s
DOUT_19_16 : GPIO_REGS_s
dout_2 : GPIO_DOUT_3_0_REG_s
dout_20 : GPIO_DOUT_23_20_REG_s
dout_21 : GPIO_DOUT_23_20_REG_s
dout_22 : GPIO_DOUT_23_20_REG_s
dout_23 : GPIO_DOUT_23_20_REG_s
DOUT_23_20 : GPIO_REGS_s
dout_24 : GPIO_DOUT_27_24_REG_s
dout_25 : GPIO_DOUT_27_24_REG_s
dout_26 : GPIO_DOUT_27_24_REG_s
dout_27 : GPIO_DOUT_27_24_REG_s
DOUT_27_24 : GPIO_REGS_s
dout_28 : GPIO_DOUT_31_28_REG_s
dout_29 : GPIO_DOUT_31_28_REG_s
dout_3 : GPIO_DOUT_3_0_REG_s
dout_30 : GPIO_DOUT_31_28_REG_s
dout_31 : GPIO_DOUT_31_28_REG_s
DOUT_31_28 : GPIO_REGS_s
DOUT_3_0 : GPIO_REGS_s
dout_4 : GPIO_DOUT_7_4_REG_s
dout_5 : GPIO_DOUT_7_4_REG_s
dout_6 : GPIO_DOUT_7_4_REG_s
dout_7 : GPIO_DOUT_7_4_REG_s
DOUT_7_4 : GPIO_REGS_s
dout_8 : GPIO_DOUT_11_8_REG_s
dout_9 : GPIO_DOUT_11_8_REG_s
DOUT_CLR : GPIO_REGS_s
dout_clr : GPIO_DOUT_CLR_REG_s
DOUT_EN : GPIO_REGS_s
dout_en : GPIO_DOUT_EN_REG_s
DOUT_EN_CLR : GPIO_REGS_s
dout_en_clr : GPIO_DOUT_EN_CLR_REG_s
DOUT_EN_SET : GPIO_REGS_s
dout_en_set : GPIO_DOUT_EN_SET_REG_s
DOUT_SET : GPIO_REGS_s
dout_set : GPIO_DOUT_SET_REG_s
DOUT_TGL : GPIO_REGS_s
dout_tgl : GPIO_DOUT_TGL_REG_s
dow : RTC_DOW_CTL_REG_s
DOW_CTL : RTC_REGS_s
dow_rtc_rdy : RTC_DOW_CTL_REG_s
drive_strength : IOMUX_PA_REG_s
DSPI_CTRL : SPI_REGS_s
dspi_first : SPI_DSPI_CTRL_REG_s
dst_addr : dma_channel_cfg_t
dst_inc : dma_mem_ctrl_cfg_t, DMA_STRIDE_MODE_CFG_0_REG_s
dst_incr : dma_channel_cfg_t
dst_prot_ctrl : dma_channel_cfg_t, dma_mem_ctrl_cfg_t
dst_size : dma_channel_cfg_t, dma_mem_ctrl_cfg_t
dst_stride_val : DMA_STRIDE_MODE_CFG_0_REG_s
dummy : IOMUX_DUMMY_REG_s
DUMMY0 : IOMUX_REGS_s
DUMMY1 : IOMUX_REGS_s